Reverse-conducting insulated gate bipolar transistor and diode with one structure semiconductor device
In the reverse-conducting IGBT according to the present invention, an n-type buffer layer surrounds a p-type collector layer. A p-type separation layer surrounds an n-type cathode layer. The n-type buffer layer separates the p-type collector layer and the p-type separation layer from each other. The p-type separation layer separates the n-type cathode layer and the n-type buffer layer from each other. Therefore, the present invention makes it possible to reduce snapback.
1. A semiconductor device comprising:
an n-type drift layer;
a p-type base layer in a channel region on the n-type drift layer;
an n-type emitter layer on the p-type base layer;
a trench-gate electrode penetrating the p-type base layer and the n-type emitter layer and being in contact with the p-type base layer and the n-type emitter layer through a gate insulating film;
a p-type anode layer in a region other than the channel region on the n-type drift layer;
an emitter electrode connected to the n-type emitter layer and the p-type anode layer;
a p-type collector layer below the n-type drift layer;
an n-type cathode layer below the n-type drift layer;
a collector electrode connected to the p-type collector layer and the n-type cathode layer;
an n-type buffer layer surrounding the p-type collector layer; and
a p-type separation layer surrounding the n-type cathode layer,
wherein the n-type buffer layer separates the p-type collector layer and the p-type separation layer from each other, and
the p-type separation layer separates the n-type cathode layer and the n-type buffer layer from each other.
2. The semiconductor device according to claim 1 , wherein in a region between the p-type collector layer and the n-type cathode layer, impurity concentration on surfaces of the n-type buffer layer and the p-type separation layer in contact with the collector electrode is lower than peak concentration of each of the n-type buffer layer and the p-type separation layer.
3. The semiconductor device according to claim 1 , wherein an interval between the p-type collector layer and the n-type cathode layer is 2 μm or less.
4. The semiconductor device according to claim 1 , wherein a width of the p-type collector layer is larger than a width of the n-type cathode layer.
5. The semiconductor device according to claim 1 , further comprising an emitter connection resistor connected between the emitter electrode and the n-type emitter layer.
6. The semiconductor device according to claim 5 , further comprising a first contact hole connecting the n-type emitter layer to the emitter electrode, and a second contact hole connecting the p-type base layer to the emitter electrode,
wherein the first contact hole and the second contact hole are separated from each other.
7. The semiconductor device according to claim 5 , wherein surface concentration of the n-type emitter layer is lower than peak concentration of the n-type emitter layer.
8. The semiconductor device according to claim 1 , wherein at least a part of the n-type cathode layer is arranged immediately below the p-type anode layer.
9. The semiconductor device according to claim 1 , wherein one p-type anode layer is provided for the plurality of channel regions.
10. The semiconductor device according to claim 1 , further comprising a p-type well layer in a terminal region and connected to the emitter electrode,
wherein the n-type cathode layer is not provided immediately below the p-type well layer.
11. The semiconductor device according to claim 1 , further comprising a p-type well layer in a terminal region and connected to the emitter electrode, and an embedded oxide film provided between the n-type drift layer and the collector electrode immediately below the p-type well layer.
12. The semiconductor device according to claim 10 , further comprising an emitter connection resistor connected between the emitter electrode and the p-type well layer.