Memory system including key-value store
According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes a first memory, a control circuit and a second memory. The first memory is configured to contain a data area for storing data, and a table area containing the key-value data. The control circuit is configured to perform write and read to the first memory by addressing, and execute a request based on the key-value store. The second memory is configured to store the key-value data in accordance with an instruction from the control circuit. The control circuit performs a set operation by using the key-value data stored in the first memory, and the key-value data stored in the second memory.
1. A system comprising:
a first memory device storing data and key-value data including at least one pair of a key and a value corresponding to the key;
a second memory device; and
a control circuit, communicating with the first memory device and the second memory device, and performing a set operation using the key-value data stored in the first memory device and using the second memory device, the set operation including a first instruction and a second instruction,
wherein,
the control circuit performs the set operation using the key and the value corresponding to the key,
the control circuit issues the first instruction to the first memory device and issues the second instruction to the second memory device,
the second memory device stores the key-value data in response to the second instruction from the control circuit, and
the set operation produces an answer comprising at least the value.
2. The system according to claim 1 , wherein
the key-value data includes a first address, a first key and a first value corresponding to the first key, the first key and the first value being stored at the first address, a second address being stored in the first value, and
a second value is obtained by referring to a storage location in the first memory device, which is designated by the second address.
3. The system according to claim 2 , further comprising a hash generator converting the first key into the first address by using a hash function.
4. The system according to claim 1 , wherein the first memory device comprises a DRAM.
5. The system according to claim 2 , wherein the first memory device comprises:
a content addressable memory (CAM) comparing the first key with data stored in the first memory device in response to input of the first key, and output a third address at which data matching the first key is stored; and
a RAM undergoing a write and read by designating the third address.
6. The system according to claim 1 , wherein the second memory device comprises a main memory controlled by the control circuit.
7. The system according to claim 6 , wherein the main memory comprises a DRAM.
8. The system according to claim 2 , wherein the second memory device comprises:
a content addressable memory (CAM) comparing the first key with data stored in the second memory device in response to input of the first key, and output a third address at which data matching the first key is stored; and
a RAM undergoing a write and read by designating the third address.
9. The system according to claim 8 , wherein the second memory device comprises a NAND flash memory.
10. The system according to claim 1 , further comprising a memory controller connected between the control circuit and the first memory device,
wherein the memory controller comprises a direct memory access (DMA) circuit, and the direct memory access (DMA) circuit controls the second memory device without the control circuit.
11. The system according to claim 1 , wherein the control circuit varies a memory capacity of the key-value data formed in the first memory device, in accordance with a request based on the key-value data.
12. The system according to claim 1 , wherein the control circuit comprises a CPU connected to the first memory device and the second memory device via a bus.
13. The system according to claim 1 , wherein the set operation performed by the control circuit includes at least one of AND, OR, and NOT.