Integrated circuit testing with power collapsed
Provided are apparatus and methods for testing an integrated circuit. In an exemplary method for testing an integrated circuit, a test controller and a power manager are integrated into a main power domain of the integrated circuit. The test controller can be Joint Test Action Group-compatible. An isolation signal is generated using the power manager. The isolation signal can comprise at least one of a freeze signal configured to isolate an input-output port of the integrated circuit, and a clamp signal configured to isolate a functional module of the integrated circuit. The isolation signal can be stored in a boundary scan register controlled with the test controller. The main power domain is isolated from a power-collapsible domain of the integrated circuit with the isolation signal. Power of the power-collapsible domain is collapsed. When power is collapsed, the power-collapsible domain is tested using the test controller and the power manager. The testing of the power-collapsible domain can comprise testing a power supply current. When power to the power-collapsible domain is collapsed, a level shifter output can be held constant to an output level based on a pre-collapse input from the power-collapsible domain.
1. A method for testing an integrated circuit, comprising:
integrating a test controller and a power manager into a main power domain of the integrated circuit;
generating an isolation signal using the power manager;
isolating the main power domain from a power-collapsible domain of the integrated circuit with the isolation signal;
collapsing power of the power-collapsible domain; and
testing the power-collapsible domain, when the power is collapsed, using the test controller and the power manager.
2. The method of claim 1 , wherein the test controller is Joint Test Action Group-compatible.
3. The method of claim 1 , wherein the isolation signal comprises at least one of a freeze signal configured to isolate an input-output port of the integrated circuit, and a clamp signal configured to isolate a functional module of the integrated circuit.
4. The method of claim 1 , further comprising storing the isolation signal in a boundary scan register, and controlling the boundary scan register with the test controller.
5. The method of claim 1 , wherein the testing the power-collapsible domain comprises testing a power supply current.
6. The method of claim 1 , further comprising holding constant, when the power to the power-collapsible domain is collapsed, a level shifter output to an output level based on a pre-collapse input from the power-collapsible domain.
7. An integrated circuit, comprising:
a test controller and a power manager in a main power domain of the integrated circuit;
means for generating an isolation signal;
means for isolating the main power domain from a power-collapsible domain of the integrated circuit;
means for collapsing power of the power-collapsible domain; and
means for testing the power-collapsible domain when the power is collapsed.
8. The integrated circuit of claim 7 , wherein the test controller is Joint Test Action Group-compatible.
9. The integrated circuit of claim 7 , wherein the means for isolating includes means for generating an isolation signal comprising a freeze signal configured to isolate an input-output port of the integrated circuit, a clamp signal configured to isolate a functional module of the integrated circuit, or both.
10. The integrated circuit of claim 7 , further comprising means for storing the isolation signal in a boundary scan register, and means for controlling the boundary scan register with the test controller.
11. The integrated circuit of claim 7 , wherein the means for testing the power-collapsible domain comprises means for testing a power supply current.
12. The integrated circuit of claim 7 , further comprising a level shifter coupled to the test controller, wherein the level shifter:
has an input coupled to the power-collapsible domain,
has an output coupled to the main power domain, and
is configured to hold constant, when the power to the power-collapsible domain is collapsed, the level shifter output to an output level based on a pre-collapse input from the power-collapsible domain.
13. A non-transitory computer-readable medium, comprising:
computer-executable instructions stored thereon that cause a lithographic device to fabricate at least a part of an integrated circuit including:
a test controller configured to test a power-collapsible domain when power is collapsed; and
a power manager in a main power domain of the integrated circuit, wherein the power manager is configured to generate an isolation signal to isolate the main power domain from the power-collapsible domain of the integrated circuit, to collapse power of the power-collapsible domain, and to test the power-collapsible domain when the power is collapsed.
14. The integrated circuit of claim 13 , wherein the test controller is Joint Test Action Group-compatible.
15. The integrated circuit of claim 13 , wherein the isolation signal comprises at least one of a freeze signal configured to isolate an input-output port of the integrated circuit, and a clamp signal configured to isolate a functional module of the integrated circuit.
16. The integrated circuit of claim 13 , further comprising a boundary scan register configured to store the isolation signal, wherein the test controller is configured to control the boundary scan register.
17. The integrated circuit of claim 13 , wherein the power manager is configured to test a power supply current.
18. The integrated circuit of claim 13 , further comprising a level shifter coupled to the test controller, wherein the level shifter has an input coupled to the power-collapsible domain, has an output coupled to the main power domain, and is configured to hold constant, when the power to the power-collapsible domain is collapsed, the level shifter output to an output level based on a pre-collapse input from the power-collapsible domain.