Processing device with self-scrubbing logic

1. An apparatus comprising:

a processing unit including:

configuration memory; and

self-scrubber logic coupled to read the configuration memory to detect compromised data stored in the configuration memory;

a watchdog unit external to the processing unit and coupled to the self-scrubber logic to detect a failure in the self-scrubber logic, wherein the watchdog unit is coupled to the processing unit to selectively reset the processing unit in response to detecting the failure in the self-scrubber logic; and

an external memory external to the processing unit and coupled to send configuration data to the configuration memory in response to a data feed signal outputted by the self-scrubber logic.

2. The apparatus of claim 1 , wherein, in response to detecting compromised data in the configuration memory, the self-scrubber logic is coupled to rewrite substantially all of the configuration memory when the compromised data includes a threshold level of flipped bits and coupled to correct a targeted portion of the configuration memory when the compromised data includes less than the threshold level of flipped bits.

3. The apparatus of claim 2 , wherein the self-scrubber logic is coupled to output the data feed signal to the external memory when the compromised data includes the threshold level of flipped bits, and wherein the external memory is coupled to load a bitfile into the configuration memory in response to receiving the data feed signal from the self-scrubber logic.

4. The apparatus of claim 2 , wherein the targeted portion of the configuration memory is a frame, and wherein the self-scrubber logic is coupled to write over the frame with a golden frame when the frame includes less than the threshold level of flipped bits, the frame once containing the same data as the golden frame.

5. The apparatus of claim 4 , wherein the golden frame is stored in the external memory.

6. The apparatus of claim 2 , wherein the targeted portion of the configuration memory is one bit within a frame, and wherein self-scrubber logic is coupled to flip the bit when the frame includes less than the threshold level of flipped bits, the threshold level of flipped bits being two flipped bits within a given frame of memory.

7. The apparatus of claim 2 , wherein the threshold level of flipped bits is two flipped bits in a frame of compromised data of the configuration memory.

8. The apparatus of claim 1 , wherein the self-scrubber is coupled to cycle through frames of the configuration memory frame-by-frame by calculating a syndrome for each frame, wherein the syndrome is calculated to be zero when no error exists in the frame.

9. The apparatus of claim 1 , wherein the self-scrubber logic is coupled to periodically output a heartbeat pulse to the watchdog unit to indicate the self-scrubber logic has not failed, and wherein the watchdog unit is coupled to the processing unit to selectively reset the processing unit in response to not receiving the heartbeat signal during a pre-determined period of time.

10. The apparatus of claim 9 , wherein the watchdog unit includes a timer coupled to be reset by the heartbeat pulse, and wherein watchdog unit is coupled to reset the processing unit when the timer reaches a pre-determined count associated with the pre-determined period of time.

11. The apparatus of claim 1 , wherein the external memory is radiation hardened by design (“RHBD”) non-volatile memory.

12. The apparatus of claim 1 , wherein the processing unit is a reprogrammable field-programmable-gate-array (“FPGA”).

13. The apparatus of claim 1 , wherein the configuration memory includes FLASH memory.