Adaptive data prefetching

1. A method, comprising:

determining a value for a stride length (L) in response to detecting a stride pattern in memory operations;

prefetching data for expected memory operations based on a prefetch address determined based on a base memory address, the stride length L, and a prefetch distance (D), wherein the prefetch address is given by a sum of the base memory address and a product (L×D);

maintaining a miss prefetch count (C) indicative of a number of prefetch misses for prefetched memory operations; and

adaptively modifying the prefetch distance D when the miss prefetch count C reaches a count threshold (T), including incrementing the prefetch distance D, and not incrementing the prefetch distance D when a maximum prefetch distance extending to a size of a memory page is attained, and further comprising:

comparing the prefetch address determined to a maximum threshold and, when the prefetch address determined exceeds the maximum threshold, using the maximum threshold as the prefetch address.

2. The method of claim 1 , further comprising:

resetting the miss prefetch count C to zero and the prefetch distance D to one when the stride pattern is no longer detected.

3. The method of claim 1 , wherein the maintaining of the miss prefetch count C comprises:

maintaining an instruction pointer prefetch array including an instance of a miss prefetch count C for each prefetch address value in the prefetch array.

4. The method of claim 1 , wherein the stride pattern is indicative of a fixed memory address offset between successive memory operations.

5. The method of claim 4 , wherein the fixed memory address offset is used for the stride length L.

6. The method of claim 1 , wherein the base memory address is indicated by an instruction referenced by an instruction pointer.

7. The method of claim 1 , further comprising preventing data at a first prefetch address from being prefetched, when the data at the first prefetch address is stored in a cache memory.

8. A processor, comprising:

a data prefetch unit to:

determine a stride length (L) in response to detection of a stride pattern in memory operations;

prefetch data for expected memory operations based on a prefetch address determined based on a base memory address, the stride length L, and a prefetch distance (D), wherein the prefetch address is given by a sum of the base memory address and a product (L×D);

maintain a miss prefetch count (C) indicative of a number of prefetch misses for prefetched memory operations; and

when the miss prefetch count C equals a count threshold (T), modify the prefetch distance D, including incrementation of the prefetch distance D, and to not increment the prefetch distance D when a maximum prefetch distance extending to a size of a memory page is attained, and further comprising:

comparison of the prefetch address determined to a maximum threshold and, when the prefetch address determined exceeds the maximum threshold, use the maximum threshold as the prefetch address.

9. The processor of claim 8 , wherein the data prefetch unit is operable to:

when the stride pattern is no longer detected:

reset the miss prefetch count C to zero and the prefetch distance D to one.

10. The processor of claim 8 , wherein the data prefetch unit is operable to initialize a value for the count threshold T.

11. The processor of claim 8 , wherein the data prefetch unit is operable to:

maintain an instruction pointer prefetch array with an instance of the miss prefetch count C for each prefetch address value.

12. The processor of claim 8 , wherein the stride pattern is indicative of a fixed memory address offset between successive memory operations.

13. The processor of claim 12 , wherein the fixed memory address offset is used for the stride length L.

14. The processor of claim 8 , wherein the base memory address is indicated by an instruction referenced by an instruction pointer.

15. A system comprising:

a processor;

a memory accessible to the processor;

a touchscreen controller; and

wherein the processor includes an adaptive data prefetch unit to:

determine a value for a stride length (L) responsive to detection of a stride pattern in memory operations;

prefetch data for expected memory operations based on a prefetch address determined based on a base memory address, the stride length L, and a prefetch distance (D), wherein the prefetch address is given by a sum of the base memory address and a product (L×D);

count a number of prefetch misses as a miss prefetch count (C) for prefetched memory operations; and

when the miss prefetch count C equals a count threshold (T), modify the prefetch distance D, including incrementation of the prefetch distance D, and to not increment the prefetch distance D when a maximum prefetch distance extending to a size of a memory page is attained, and further comprising:

comparison of the prefetch address determined to a maximum threshold and, when the prefetch address determined exceeds the maximum threshold, use the maximum threshold as the prefetch address.

16. The system of claim 15 , wherein the adaptive prefetch unit is operable to:

when the stride pattern is no longer detected:

reset the miss prefetch count C to zero and the prefetch distance D to one.

17. The system of claim 15 , wherein the adaptive prefetch unit is operable to initialize a value for the count threshold T.

18. The system of claim 15 , wherein the processor is operable to:

maintain an instruction pointer prefetch array with an instance of the miss prefetch count C for each prefetch address value.

19. The system of claim 15 , wherein the stride pattern is indicative of a fixed memory address offset between successive memory operations.

20. The system of claim 19 , wherein the fixed memory address offset is used for the stride length L.

21. The system of claim 15 , wherein the base memory address is indicated by an instruction referenced by an instruction pointer.