Systems and methods for support of non-volatile memory on a DDR memory channel

1. An information handling system, comprising:

at least one host processing device configured to execute an operating system (OS) and one or more OS write drivers configured to manage writes; and

a double data rate (DDR)-based non-volatile memory (NVM) system comprising one or more NVM devices coupled to the host processing device through a memory buffer that includes write buffer circuitry, the memory buffer being coupled to the host processing device by a DDR memory channel and the memory buffer being coupled to the DDR-based NVM system by a NVM channel;

where the host processing device is configured to access the DDR-based NVM system across the DDR memory channel for data read and data write operations through the memory buffer and the NVM channel;

where the memory buffer is configured to respond to receipt of standard DDR read commands received across the DDR memory channel from the host processing device by performing direct reads of data stored on the NVM memory devices across the NVM channel, and providing the read data directly from the NVM channel directly to the DDR memory channel by a direct read path that is within the memory buffer but not through the write buffer circuitry to the host processing device across the DDR memory channel; and

where the memory buffer is configured to respond to receipt of write commands received across the DDR memory channel from the OS write drivers of the host processing device by performing indirect writes of data to the NVM memory devices across the NVM channel.

2. The system of claim 1 , where the memory buffer is configured to respond to receipt of standard DDR read commands received across the DDR memory channel from the host processing device by performing direct program level semantic memory reads of data stored on the NVM memory devices across the NVM channel with no OS driver calls, and providing the read data to the host processing device across the DDR memory channel; and where the memory buffer is configured to respond to receipt of a series of DDR write commands received across the DDR memory channel from the OS write drivers of the host processing device by performing indirect writes of data to the NVM memory devices across the NVM channel in response to one or more OS driver calls.

3. The system of claim 1 , where the memory buffer is configured to respond to receipt of standard DDR read commands received across the DDR memory channel from the host processing device by performing direct program level semantic memory reads of data stored on the NVM memory devices across the NVM channel, and providing the read data to the host processing device across the DDR memory channel; and where the memory buffer is configured to respond to receipt of write commands received across the DDR memory channel using command semantics layered on top of DDR protocol.

4. The system of claim 1 , where the memory buffer is configured to respond to receipt of a series of DDR write commands received across the DDR memory channel by deriving and issuing a corresponding series of NVM write commands to the DDR-based non-volatile memory system across the NVM channel, the series of DDR write commands being different than the corresponding series of DDR write commands that were received across the DDR memory channel.

5. The system of claim 1 , where the NVM memory devices comprise Phase Change Memory (PCM)-based memory devices.

6. The system of claim 1 , where the DDR memory channel comprises a DDR command channel and a DDR data channel; where the NVM channel comprises a NVM command channel and a NVM data channel; where the memory buffer comprises at least one processing device coupled to input/output multiplexer circuitry, the input/output multiplexer circuitry being coupled between the DDR data channel and the NVM data channel; and where the processing device is configured to control circuitry of the memory buffer to:

receive a read command from the host processing device across the DDR command channel, the read command including a random access memory address designating one or more of the NVM devices;

in response to the received read command, submitting a read command to the random access address of the designated NVM devices across the NVM command channel; and

receive read data at the input/output multiplexer circuitry from the NVM devices from across the NVM data channel corresponding to the read command submitted across the NVM command channel;

where the processing device is further configured to provide control signals to configure the input/output multiplexer to transmit the read data received from the NVM devices by a direct read path through the memory buffer from the NVM data channel via the DDR data channel to the host processing device.

7. The system of claim 6 , where the command register circuitry and write buffer circuitry are each coupled to the input/output multiplexer circuitry; and where the processing device is further configured to control circuitry of the memory buffer to:

receive a series of DDR write commands from the OS write drivers of the host processing device across the DDR command channel, the DDR write commands targeting command sections of a designated one or more of the NVM memory devices;

receive at the input/output multiplexer circuitry a series of NVM write commands from the OS write drivers of the host processing device across the DDR data channel coincident with the DDR write commands received across the DDR command channel; and

receive write data at the input/output multiplexer circuitry across the DDR data channel to be written to the designated NVM memory devices;

where in response to the DDR write commands received across the DDR command channel the processing device is further configured to provide control signals to configure the input/output multiplexer to provide the received write data to the write buffer circuitry and to provide the received NVM write commands to the command register circuitry;

where the write buffer circuitry is configured to provide the received write data to the designated NVM memory devices across the NVM data channel; and

where coincident with the write data provided to the designated NVM memory devices, the command register circuitry is configured to forward write requests corresponding to the received NVM write commands to the designated NVM memory devices across the NVM command channel to cause the write data to be written to the designated NVM memory devices.

8. The system of claim 1 , where the DDR memory channel comprises a DDR command channel and a DDR data channel; where the NVM channel comprises a NVM command channel and a NVM data channel; where the memory buffer comprises at least one processing device; where the at least one processing device, command register circuitry, and write buffer circuitry are each coupled to input/output multiplexer circuitry, the input/output multiplexer circuitry being coupled between the DDR data channel and the NVM data channel; and where the processing device is configured to control circuitry of the memory buffer to:

receive a series of DDR write commands from the OS write drivers of the host processing device across the DDR command channel, the DDR write commands targeting a command section of a designated one or more of the NVM memory devices;

receive at the input/output multiplexer circuitry a series of NVM write commands from the OS write drivers of the host processing device across the DDR data channel coincident with the DDR write commands received across the DDR command channel; and

receive write data at the input/output multiplexer circuitry across the DDR data channel to be written to the designated NVM memory devices;

where in response to the DDR write commands received across the DDR command channel the processing device is further configured to provide control signals to configure the input/output multiplexer to provide the received write date to the write buffer circuitry and to provide the received NVM write commands to the command register circuitry;

where the write buffer circuitry is configured to forward the received write data to the designated NVM memory devices across the NVM data channel; and

where coincident with the write data forwarded to the designate NVM memory devices, the command register circuitry is configured to forward write requests corresponding to the received NVM write commands to the designated NVM memory devices across the NVM command channel to cause the write data to be written to the designated NVM memory devices.

9. The system of claim 8 , where the memory buffer further comprises status register circuitry coupled to input/output multiplexer circuitry; and where the processing device is configured to control circuitry of the memory buffer to:

receive a status check read operation across the DDR command channel from the host processing device after the write data is written to the designated NVM memory devices;

in response to the received read command, provide control signals to configure the input/output multiplexer to provide status information regarding the previous write of data to the designated NVM memory devices from the status register circuitry to the host processing device across the DDR data channel.

10. The system of claim 1 , further comprising:

at least one DDR-based volatile random access memory (RAM) system comprising one or more RAM devices coupled to the host processing device through the memory buffer, the memory buffer being coupled to the host processing device by a first DDR memory channel and the memory buffer being coupled to the DDR-based volatile RAM system by a second DDR channel;

where the host processing device is configured to access the DDR-based volatile system across the first and second DDR memory channels for data read and data write operations through the memory buffer;

where the memory buffer is configured to respond to receipt of standard DDR read commands received across the first DDR memory channel from the host processing device by performing direct reads of data stored on the volatile RAM memory devices across the second DDR channel, and providing the read data to the host processing device across the first DDR memory channel;

where the memory buffer is configured to respond to receipt of write commands received across the first DDR memory channel by performing direct writes of data to the volatile RAM memory devices across the second DDR channel.

11. A method for reading and writing data to a double data rate (DDR)-based non-volatile memory (NVM) system, the method comprising:

providing at least one host processing device configured to execute an operating system (OS) and one or more OS write drivers configured to manage writes;

providing a double data rate (DDR)-based non-volatile memory (NVM) system comprising one or more NVM devices coupled to the host processing device through a memory buffer that includes write buffer circuitry, the memory buffer being coupled to the host processing device by a DDR memory channel and the memory buffer being coupled to the DDR-based NVM system by a NVM channel;

accessing the DDR-based NVM system across the DDR memory channel using the host processing device for data read and data write operations through the memory buffer and the NVM channel;

responding to receipt of standard DDR read commands received across the DDR memory channel in the memory buffer from the host processing device by performing direct reads of data stored on the NVM memory devices across the NVM channel, and providing the read data directly from the NVM channel directly to the DDR memory channel by a direct read path that is within the memory buffer but not through the write buffer circuitry to the host processing device across the DDR memory channel; and

responding to receipt of write commands received across the DDR memory channel in the memory buffer from the OS write drivers of the host processing device by performing indirect writes of data to the NVM memory devices across the NVM channel.

12. The method of claim 11 , further comprising responding to receipt of standard DDR read commands received in the memory buffer across the DDR memory channel from the host processing device by performing direct program level semantic memory reads of data stored on the NVM memory devices across the NVM channel with no OS driver calls, and providing the read data to the host processing device across the DDR memory channel; and responding to receipt of a series of DDR write commands received across the DDR memory channel in the memory buffer from the OS write drivers of the host processing device by performing indirect writes of data to the NVM memory devices across the NVM channel in response to one or more OS driver calls.

13. The method of claim 11 , further comprising responding to receipt of standard DDR read commands received across the DDR memory channel in the memory buffer from the host processing device by performing direct program level semantic memory reads of data stored on the NVM memory devices across the NVM channel, and providing the read data to the host processing device across the DDR memory channel; and responding to receipt of write commands received across the DDR memory channel in the memory buffer using command semantics layered on top of DDR protocol.

14. The method of claim 11 , further comprising responding to receipt of a series of DDR write commands received across the DDR memory channel in the memory buffer by deriving and issuing a corresponding series of NVM write commands to the DDR-based non-volatile memory system across the NVM channel using a series of DDR write commands that are different that the corresponding series of DDR write commands that were received across the DDR memory channel.

15. The method of claim 11 , where the NVM memory devices comprise Phase Change Memory (PCM)-based memory devices.

16. The method of claim 11 , where the DDR memory channel comprises a DDR command channel and a DDR data channel; where the NVM channel comprises a NVM command channel and a NVM data channel; where the memory buffer comprises at least one processing device coupled to input/output multiplexer circuitry, the input/output multiplexer circuitry being coupled between the DDR data channel and the NVM data channel; and where the method further comprises using the processing device to control circuitry of the memory buffer to:

receive a read command from the host processing device across the DDR command channel, the read command including a random access memory address designating one or more of the NVM devices;

in response to the received read command, submit a read command to the random access address of the designated NVM devices across the NVM command channel; and

receive read data at the input/output multiplexer circuitry from the NVM devices from across the NVM data channel corresponding to the read command submitted across the NVM command channel;

where the processing device is further configured to provide control signals to configure the input/output multiplexer to transmit the read data received from the NVM devices by a direct read path through the memory buffer from the NVM data channel via the DDR data channel to the host processing device.

17. The method of claim 16 , where the command register circuitry and write buffer circuitry are each coupled to the input/output multiplexer circuitry; and where the method further comprises using the processing device to control circuitry of the memory buffer to:

receive a series of DDR write commands from the OS write drivers of the host processing device across the DDR command channel, the DDR write commands targeting a command section of a designated one or more of the NVM memory devices;

receive at the input/output multiplexer circuitry a series of NVM write commands from the OS write drivers of the host processing device across the DDR data channel coincident with the DDR write commands received across the DDR command channel; and

receive write data at the input/output multiplexer circuitry across the DDR data channel to be written to the designated NVM memory devices;

where in response to the DDR write commands received across the DDR command channel the processing device is further configured to provide control signals to configure the input/output multiplexer to provide the received write date to the write buffer circuitry and to provide the received NVM write commands to the command register circuitry;

where the write buffer circuitry is configured to provide the received write data to the designated NVM memory devices across the NVM data channel; and

where coincident with the write data provided to the designate NVM memory devices, the command register circuitry is configured to forward write requests corresponding to the received NVM write commands to the designated NVM memory devices across the NVM command channel to cause the write data to be written to the designated NVM memory devices.

18. The method of claim 11 , where the DDR memory channel comprises a DDR command channel and a DDR data channel; where the NVM channel comprises a NVM command channel and a NVM data channel; where the memory buffer comprises at least one processing device; where the at least one processing device, command register circuitry, and write buffer circuitry are each coupled to input/output multiplexer circuitry, the input/output multiplexer circuitry being coupled between the DDR data channel and the NVM data channel; and where the method further comprises using the processing device to control circuitry of the memory buffer to:

receive a series of DDR write commands from the OS write drivers of the host processing device across the DDR command channel, the DDR write commands targeting a command section of a designated one or more of the NVM memory devices;

receive at the input/output multiplexer circuitry a series of NVM write commands from the OS write drivers of the host processing device across the DDR data channel coincident with the DDR write commands received across the DDR command channel; and

receive write data at the input/output multiplexer circuitry across the DDR data channel to be written to the designated NVM memory devices;

where in response to the DDR write commands received across the DDR command channel the processing device is further configured to provide control signals to configure the input/output multiplexer to provide the received write date to the write buffer circuitry and to provide the received NVM write commands to the command register circuitry;

where the write buffer circuitry is configured to forward the received write data to the designated NVM memory devices across the NVM data channel; and

where coincident with the write data forwarded to the designate NVM memory devices, the command register circuitry is configured to forward write requests corresponding to the received NVM write commands to the designated NVM memory devices across the NVM command channel to cause the write data to be written to the designated NVM memory devices.

19. The method of claim 18 , where the memory buffer further comprises status register circuitry coupled to input/output multiplexer circuitry; and where the method further comprises using the processing device to control circuitry of the memory buffer to:

receive a status check read operation across the DDR command channel from the host processing device after the write data is written to the designated NVM memory devices;

in response to the received read command, provide control signals to configure the input/output multiplexer to provide status information regarding the previous write of data to the designated NVM memory devices from the status register circuitry to the host processing device across the DDR data channel.

20. The method of claim 11 , further comprising:

providing at least one DDR-based volatile random access memory (RAM) system comprising one or more RAM devices coupled to the host processing device through the memory buffer, the memory buffer being coupled to the host processing device by a first DDR memory channel and the memory buffer being coupled to the DDR-based volatile RAM system by a second DDR channel;

accessing the DDR-based volatile RAM system across the first DDR memory channel using the host processing device for data read and data write operations through the memory buffer and the second DDR memory channel;

responding to receipt of standard DDR read commands received across the first DDR memory channel in the memory buffer from the host processing device by performing direct reads of data stored on the volatile RAM devices across the second DDR channel, and providing the read data to the host processing device across the first DDR memory channel;

responding to receipt of write commands received across the first DDR memory channel in the memory buffer from the host processing device by performing direct writes of data to the volatile RAM memory devices across the second DDR channel.

21. The system of claim 1 , where the memory buffer comprises input/output multiplexer circuitry coupled between the DDR data channel and the NVM data channel; and input output (IO) physical layer transceiver circuitry coupled between the input/output multiplexer circuitry and the NVM data channel; and where the memory buffer is further configured to respond to receipt of standard DDR read commands received across the DDR memory channel from the host processing device by performing direct reads of data stored on the NVM memory devices across the NVM channel, and providing the read data directly from the NVM channel directly to the DDR memory channel by a direct read path between the input output (TO) physical layer transceiver circuitry and the input/output multiplexer circuitry to the host processing device across the DDR memory channel.

22. The method of claim 11 , where the memory buffer comprises input/output multiplexer circuitry coupled between the DDR data channel and the NVM data channel; and input output (IO) physical layer transceiver circuitry coupled between the input/output multiplexer circuitry and the NVM data channel; and where the method further comprises responding to receipt of standard DDR read commands received across the DDR memory channel in the memory buffer from the host processing device by performing direct reads of data stored on the NVM memory devices across the NVM channel, and providing the read data directly from the NVM channel directly to the DDR memory channel by a direct read path between the input output (IO) physical layer transceiver circuitry and the input/output multiplexer circuitry to the host processing device across the DDR memory channel.

23. An information handling system, comprising:

at least one first processing device configured as a host processing device to execute an operating system (OS); and

a double data rate (DDR)-based non-volatile memory (NVM) system comprising one or more NVM devices coupled to the host processing device through a second processing device, the second processing device being coupled to the host processing device by a DDR memory channel and the second processing device being coupled to the DDR-based NVM system by a NVM channel;

where the host processing device and second processing device are configured to perform a direct read operation of data stored on the NVM memory devices using a single DDR read command transaction that includes the following sequence of steps:

the host processing device being configured to provide a single standard DDR read command across the DDR memory channel from the host processing device to the second processing device, the DDR read command including a random access memory address designating one or more of the NVM devices; and

the second processing device being configured to then respond to receipt of the single standard DDR read command at the second processing device by submitting a read command from the second processing device to the random access address of the designated NVM devices across the NVM command channel;

the second processing device being configured to then receive read data from the NVM devices at the second processing device from across the NVM data channel, the read data corresponding to the read command submitted across the NVM command channel; and

the second processing device being configured to then transmit the received read data from the second processing device to the host processing device to complete the direct read operation.

24. The system of claim 23 , further comprising write buffer circuitry and command registers coupled to the second processing device; where the host processing device is further configured to execute one or more OS write drivers to manage writes; and where the host processing device and second processing device are further configured to perform an indirect write operation of data to the NVM memory devices across the NVM channel in response to OS driver calls by a series of multiple DDR read command transactions that includes the following sequence of steps:

the host processing device being configured to provide a series of multiple DDR write commands and corresponding write data from the OS write drivers of the host processing device to the second processing device, the DDR write commands including corresponding NVM write commands;

the second processing device being configured to then respond to receipt of the series of multiple DDR write commands and corresponding write data and NVM write commands received across the DDR memory channel from the OS write drivers of the host processing device by writing received write data from each of the multiple DDR write commands to the write buffer circuitry and writing received NVM write commands from each of the multiple DDR write commands to the command registers; and

the second processing device being configured to then perform the steps of issuing write commands from the command registers to the NVM devices across the NVM command channel and transmitting the corresponding write data to the NVM devices across the NVM data channel to complete the indirect write operation, only after writing the received write data from each of the multiple DDR write commands to the write buffer circuitry and only after writing the received NVM write commands from each of the multiple DDR commands to the command registers.

25. A method for reading data from a double data rate (DDR)-based non-volatile memory (NVM) system, the method comprising:

providing at least one first processing device configured as a host processing device to execute an operating system (OS);

providing a double data rate (DDR)-based non-volatile memory (NVM) system comprising one or more NVM devices coupled to the host processing device through at least one second processing device that is coupled to the host processing device by a DDR memory channel and that is coupled to the DDR-based NVM system by a NVM channel;

performing a direct read operation of data stored on the NVM memory devices using a single DDR read command transaction that includes the following sequence of steps:

using the host processing device to provide a single standard DDR read command across the DDR memory channel from the host processing device to the second processing device, the DDR read command including a random access memory address designating one or more of the NVM devices; and

then using the second processing device to respond to receipt of the single standard DDR read command at the second processing device by submitting a read command from the second processing device to the random access address of the designated NVM devices across the NVM command channel;

then using the second processing device to receive read data from the NVM devices at the second processing device from across the NVM data channel, the read data corresponding to the read command submitted across the NVM command channel; and

then using the second processing device to transmit the received read data from the second processing device to the host processing device to complete the direct read operation.

26. The method of claim 25 , further comprising

providing write buffer circuitry and command registers coupled to the second processing device;

using the host processing device to execute one or more OS write drivers to manage writes; and

performing an indirect write operation of data to the NVM memory devices across the NVM channel in response to OS driver calls by a series of multiple DDR read command transactions that includes the following sequence of steps:

using the host processing device to provide a series of multiple DDR write commands and corresponding write data from the OS write drivers of the host processing device to the second processing device, the DDR write commands including corresponding NVM write commands;

then using the second processing device to respond to receipt of the series of multiple DDR write commands and corresponding write data and NVM write commands received across the DDR memory channel from the OS write drivers of the host processing device by writing received write data from each of the multiple DDR write commands to the write buffer circuitry and writing received NVM write commands from each of the multiple DDR write commands to the command registers; and

then using the second processing device to perform the steps of issuing write commands from the command registers to the NVM devices across the NVM command channel and transmitting the corresponding write data to the NVM devices across the NVM data channel to complete the indirect write operation, only after writing the received write data from each of the multiple DDR write commands to the write buffer circuitry and only after writing the received NVM write commands from each of the multiple DDR commands to the command registers.