Transistor having reduced channel length
View Patent ↗A transistor which includes an oxide semiconductor and can operate at high speed is provided. A highly reliable semiconductor device including the transistor is provided. An oxide semiconductor layer including a pair of low-resistance regions and a channel formation region is provided over an electrode layer formed in a groove of a base insulating layer. The channel formation region is embedded in a position overlapping with a gate electrode which has a side surface provided with a sidewall. The groove includes a deep region and a shallow region. The sidewall overlaps with the shallow region, and a connection portion between a wiring and the electrode layer overlaps with the deep region.
1. A semiconductor device comprising:
a semiconductor substrate;
an insulating layer over the semiconductor substrate, the insulating layer comprising a groove in which a conductive film comprising a first region and a second region is provided;
an oxide semiconductor film comprising a third region and a fourth region over a top surface of the insulating layer;
a gate insulating layer over the oxide semiconductor film;
a gate electrode over the gate insulating layer, the gate electrode overlapping with the third region; and
a sidewall in contact with a side surface of the gate electrode and a top surface of the gate insulating layer,
wherein the second region is over the first region,
wherein a width of the second region is greater than a width of the first region, and
wherein the fourth region is over and in contact with the second region.
2. The semiconductor device according to claim 1 , wherein a conductive layer is in contact with the sidewall and the oxide semiconductor film.
3. The semiconductor device according to claim 1 , further comprising:
an interlayer insulating layer over the gate electrode; and
a wiring over the interlayer insulating layer,
wherein the wiring is electrically connected to the conductive film.
4. The semiconductor device according to claim 1 , wherein the oxide semiconductor film contains indium, gallium, and zinc.
5. The semiconductor device according to claim 1 , wherein the oxide semiconductor film contains indium, tin, and zinc.
6. A semiconductor device comprising:
a semiconductor substrate;
an insulating layer over the semiconductor substrate, the insulating layer comprising a groove in which a conductive film comprising a first region and a second region is provided;
an oxide semiconductor film comprising a third region and a fourth region over a top surface of the insulating layer;
a gate insulating layer over the oxide semiconductor film;
a gate electrode over the gate insulating layer, the gate electrode overlapping with the third region; and
a sidewall in contact with a side surface of the gate electrode and a top surface of the gate insulating layer,
wherein the second region is over the first region,
wherein a width of the second region is greater than a width of the first region,
wherein the fourth region is over and in contact with the second region, and
wherein a top surface of the conductive film is a same as the top surface of the insulating layer.
7. The semiconductor device according to claim 6 , wherein a conductive layer is in contact with the sidewall and the oxide semiconductor film.
8. The semiconductor device according to claim 6 , further comprising:
an interlayer insulating layer over the gate electrode; and
a wiring over the interlayer insulating layer,
wherein the wiring is electrically connected to the conductive film.
9. The semiconductor device according to claim 6 , wherein the oxide semiconductor film contains indium, gallium, and zinc.
10. The semiconductor device according to claim 6 , wherein the oxide semiconductor film contains indium, tin, and zinc.