Stressed nanowire stack for field effect transistor
A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires. Isolated gate structures are formed in regions underlying the disposable gate structure by deposition and recessing of a first gate dielectric layer and a first gate conductor layer. After formation of a gate spacer, source regions, and drain regions, raised source and drain regions are formed on the source regions and the drain regions by selective deposition of a semiconductor material. The disposable gate structure is replaced with a replacement gate structure by deposition and patterning of a second gate dielectric layer and a second gate conductor layer. Distortion of the suspended semiconductor nanowires is prevented by the disposable gate structure and the isolated gate structures.
1. A semiconductor structure comprising:
a first semiconductor nanowire overlying a substrate;
a second semiconductor nanowire overlying said first semiconductor nanowire and vertically spaced from said first semiconductor nanowire; and
a gate structure surrounding said first and second semiconductor nanowires, wherein said gate structure includes:
a first gate dielectric contacting a bottom surface of said second semiconductor nanowire;
a second gate dielectric contacting a top surface and sidewall surfaces of said second semiconductor nanowire; and
a gate spacer including a sidewall that contacts said first gate dielectric, a horizontal surface contacting a bottom surface of said second semiconductor nanowire, and another horizontal surface contacting a top surface of said first semiconductor nanowire.
2. The semiconductor structure of claim 1 , further comprising:
a first gate electrode underlying said first gate dielectric and overlying said first semiconductor nanowire; and
a second gate electrode contacting said second gate dielectric.
3. The semiconductor structure of claim 2 , wherein said second gate electrode and said first gate electrode differ from each other by composition.
4. The semiconductor structure of claim 2 , further comprising another first gate dielectric contacting a bottom surface of said first gate electrode and a top surface of said first semiconductor nanowire.
5. The semiconductor structure of claim 2 , wherein said second gate dielectric is in physical contact with sidewalls of said first gate electrode.
6. The semiconductor structure of claim 2 , wherein said second gate electrode is in physical contact with sidewalls of said first gate electrode.
7. The semiconductor structure of claim 6 , wherein said first gate electrode comprises:
at least one metallic gate electrode portion; and
a semiconductor gate electrode portion.
8. The semiconductor structure of claim 7 , wherein said at least one metallic gate electrode portion is a single metallic gate electrode portion, and said semiconductor gate electrode portion is laterally spaced from said second gate electrode by said single metallic gate electrode portion.
9. The semiconductor structure of claim 7 , wherein said at least one metallic gate electrode portion is a pair of metallic gate electrode portions, and wherein said semiconductor gate electrode portion is in physical contact with said second gate electrode.
10. A semiconductor structure comprising:
a first semiconductor nanowire overlying a substrate;
a second semiconductor nanowire overlying said first semiconductor nanowire and vertically spaced from said first semiconductor nanowire; and
a gate structure surrounding said first and second semiconductor nanowires, wherein said gate structure includes:
a first gate dielectric contacting a bottom surface of said second semiconductor nanowire;
a second gate dielectric contacting a top surface and sidewall surfaces of said second semiconductor nanowire
a first gate electrode underlying said first gate dielectric and overlying said first semiconductor nanowire; and
a second gate electrode contacting said second gate dielectric, wherein said second gate electrode is in physical contact with sidewalls of said first gate electrode and wherein said first gate electrode comprises at least one metallic gate electrode portion, and a semiconductor gate electrode portion.
11. The semiconductor structure of claim 10 , wherein said second gate electrode and said first gate electrode differ from each other by composition.
12. The semiconductor structure of claim 10 , further comprising another first gate dielectric contacting a bottom surface of said first gate electrode and a top surface of said first semiconductor nanowire.
13. The semiconductor structure of claim 10 , wherein said at least one metallic gate electrode portion is a single metallic gate electrode portion, and said semiconductor gate electrode portion is laterally spaced from said second gate electrode by said single metallic gate electrode portion.
14. The semiconductor structure of claim 10 , wherein said at least one metallic gate electrode portion is a pair of metallic gate electrode portions, and wherein said semiconductor gate electrode portion is in physical contact with said second gate electrode.