Superstrate sub-cell voltage-matched multijunction solar cells
Voltage-matched thin film multijunction solar cell and methods of producing cells having upper CdTe pn junction layers formed on a transparent substrate which in the completed device is operatively positioned in a superstate configuration. The solar cell also includes a lower pn junction formed independently of the CdTe pn junction and an insulating layer between CdTe and lower pn junctions. The voltage-matched thin film multijunction solar cells further include a parallel connection between the CdTe pn junction and lower pn junctions to form a two-terminal photonic device. Methods of fabricating devices from independently produced upper CdTe junction layers and lower junction layers are also disclosed.
1. A voltage-matched multijunction solar cell comprising:
a CdTe pn junction layer comprising a CdTe upper sub-cell;
a lower pn junction layer comprising a lower sub-cell;
a transparent insulating layer positioned between the CdTe pn junction layer and the lower pn junction layer;
a transparent superstrate positioned opposite the CdTe pn junction layer from the transparent insulating layer; and
an interdigitated p-type and n-type back contact comprising Si and associated with the lower sub-cell on the side of the lower sub-cell opposite the transparent insulating layer,
wherein the CdTe upper sub-cell and the lower sub-cell are voltage-matched and are connected to each other in parallel.
2. The voltage-matched multijunction solar cell of claim 1 , wherein the lower pn junction layer comprises Si.
3. The voltage-matched multijunction solar cell of claim 2 , further comprising:
a transparent first front contact and a transparent first back contact associated with the CdTe upper sub-cell, wherein the transparent first back contact is positioned between the transparent insulating layer and the CdTe upper sub-cell.
4. The voltage-matched multijunction solar cell of claim 1 , wherein the lower pn junction layer is crystalline and has a thickness equal to or less than 80 micrometers.
5. The voltage-matched multijunction solar cell of claim 1 , wherein:
the CdTe upper sub-cell comprises at least one of single crystalline or polycrystalline CdTe, and
the lower sub-cell comprises at least one of single crystalline or polycrystalline Si.
6. The voltage-matched multijunction solar cell of claim 1 , wherein the CdTe pn junction layer comprises a CdTe absorber layer and a CdS emitter layer.
7. The voltage-matched multijunction solar cell of claim 1 , wherein:
the CdTe pn junction layer comprises a first string of serially connected CdTe upper sub-cells,
the lower pn junction layer comprises a second string of serially connected lower sub-cells, and
the first string and the second string are voltage-matched and are connected to each other in parallel.
8. The voltage-matched multijunction solar cell of claim 1 , wherein the transparent insulating layer comprises an oxide grown on the lower pn junction layer.
9. The voltage-matched multijunction solar cell of claim 1 , wherein the transparent superstrate comprises glass.
10. A method of fabricating a voltage-matched multijunction solar cell, the method comprising:
forming a CdTe upper sub-cell within a CdTe pn junction layer on a transparent substrate;
forming a lower sub-cell within a lower pn junction layer;
providing a transparent insulating layer between the CdTe pn junction layer and the lower pn junction layer;
forming an interdigitated p-type and n-type back contact comprising Si and associated with the lower sub-cell on the side of the lower sub-cell opposite the transparent insulating layer;
subsequently joining the CdTe pn junction layer and the lower pn junction layer such that the transparent substrate is positioned in a superstrate configuration; and
connecting the CdTe upper sub-cell and the lower sub-cell to each other in parallel, wherein the CdTe upper sub-cell and the lower sub-cell are voltage-matched.
11. The method of claim 10 , wherein the lower pn junction layer comprises Si.
12. The method of claim 11 , further comprising:
forming a transparent first front contact and a transparent first back contact associated with the CdTe upper sub-cell, wherein the transparent first back contact is positioned between the transparent insulating layer and the CdTe upper sub-cell.
13. The method of claim 10 , further comprising:
forming a transparent first front contact and a transparent first back contact associated with the CdTe upper sub-cell, wherein the transparent first back contact is positioned between the transparent insulating layer and the CdTe upper sub-cell; and
forming a transparent second front contact and a transparent second back contact associated with the lower sub-cell, wherein the transparent second front contact and the transparent second back contact are formed on opposite sides of the lower pn junction layer.
14. The method of claim 10 , wherein:
the lower sub-cell is physically supported by the transparent substrate, and
the lower pn junction layer is crystalline and has a thickness equal to or less than 80 micrometers.
15. The method of claim 10 , wherein the CdTe pn junction layer comprises a CdTe absorber layer and a CdS emitter layer.
16. The method of claim 10 , further comprising:
forming a first string of serially connected CdTe upper sub-cells within the CdTe pn junction layer;
forming a second string of serially connected Si lower sub-cells within the lower pn junction layer; and
connecting the first string and the second string to each other in parallel.
17. The method of claim 10 , wherein providing the transparent insulating layer comprises forming an oxide on the lower pn junction layer.
18. The method of claim 10 , wherein providing the transparent insulating layer comprises bonding a first side of a standalone insulating layer to the CdTe pn junction layer and bonding a second side of the standalone insulating layer opposite the first side to the lower pn junction layer.
19. The method of claim 10 , wherein the transparent insulating layer comprises polyethylene terephthalate.