IP Library Granted Patent US 9,295,035
Granted Patent B2
US 9,295,035 · App. 14/539,925 · Granted Mar 22, 2016

Method of allocating resources for transmitting uplink signal in MIMO wireless communication system and apparatus thereof

Inventors: Bong Hoe Kim (Anyang-si, KR); Dae Won Lee (Anyang-si, KR); Yu Jin Noh (Anyang-si, KR); Byeong Woo Kang (Anyang-si, KR); Dong Youn Seo (Anyang-si, KR); Dong Wook Roh (Anyang-si, KR)
Assignee: LG Electronics Inc.
H04W72/04H04B7/0413H04L5/0044H04L27/2626
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Quick Facts
Patent No.
US 9,295,035
App. No.
14/539,925
Granted
Mar 22, 2016
Kind
B2
Abstract

A method and terminal apparatus are described for allocating resources for transmitting a signal in a multiple-input multiple-output (MIMO) wireless communication system. An uplink signal is transmitted using L layers at a terminal in a multiple-input multiple-output (MIMO) wireless communication system. Modulation symbols are generated by modulating output bit sequences of an interleaver matrix by a unit of log 2 Q bits. Q is a modulation order, and each of the output bit sequences has a size of L·log 2 Q bits. The modulation symbols are mapped to the L layers and transmitted by using the L layers. The output bit sequences are generated by reading out entries of the interleaver matrix, column by column.

Claims (202)

1. A method for transmitting an uplink signal using L layers at a terminal in a multiple-input multiple-output (MIMO) wireless communication system, the method comprising:

generating, by the terminal, modulation symbols by modulating output bit sequences of an interleaver matrix by a unit of log 2 Q bits, wherein Q is a modulation order, and wherein each of the output bit sequences has a size of L*log 2 Q bits and L is a number of layers;

mapping, by the terminal, the modulation symbols to the L layers; and

transmitting, by the terminal, the modulation symbols by using the L layers.

2. The method according to claim 1 , wherein the output bit sequences are generated by reading out entries of the interleaver matrix, column by column.

3. The method according to claim 1 , wherein if a number of modulation symbols per layer is given by H and a number of columns of the interleaver matrix is given by C, a number of rows R of the interleaver matrix is defined by Equation 1 shown below:

H

·

L

·

log

2

Q

C

.

Equation

1

4. The method according to claim 3 , wherein the interleaver matrix is represented by Equation 2 shown below:

[

g

0

g

1

g

C

-

1

g

C

g

C

+

1

g

2

C

-

1

g

(

R

-

1

)

·

C

g

(

R

-

1

)

·

C

+

1

g

R

·

C

-

1

]

,

Equation

2

R

=

R

L

·

log

2

Q

wherein and g k is a vector defined by L·log 2 Q rows.

5. The method according to claim 4 , wherein the vector g k is defined by Equation 3 shown below:

g k =[q k·log 2 Q 1 , . . . ,q (k+1)·log 2 Q−1 1 ,q k·log 2 Q 2 , . . . ,q (k+1)·log 2 Q−1 2 , . . . ,q k·log 2 Q L , . . . ,q (k+1)·log 2 Q−1 L ] T ,  <Equation 3>

wherein q j denotes an encoded bit.

6. A terminal apparatus of a multiple-input multiple-output (MIMO) wireless communication system, the terminal apparatus comprising:

a processor configured to:

generate modulation symbols by modulating output bit sequences of an interleaver matrix by a unit of log 2 Q bits, wherein Q is a modulation order, and wherein each of the output bit sequences has a size of L·log 2 Q bits and L is a number of layers, and

map the modulation symbols to the L layers; and

a transmission module configured to transmit the modulation symbols by using the L layers.

7. The terminal apparatus according to claim 6 , wherein the processor is configured to generate the output bit sequences by reading out entries of the interleaver matrix, column by column.

8. The terminal apparatus according to claim 6 , wherein if a number of modulation symbols per layer is given by H and a number of columns of the interleaver matrix is given by C, a number of rows R of the interleaver matrix is defined by Equation 1 shown below:

H

·

L

·

log

2

Q

C

.

Equation

1

9. The terminal apparatus according to claim 8 , wherein the interleaver matrix is represented by Equation 2 shown below:

[

g

0

g

1

g

C

-

1

g

C

g

C

+

1

g

2

C

-

1

g

(

R

-

1

)

·

C

g

(

R

-

1

)

·

C

+

1

g

R

·

C

-

1

]

,

Equation

2

wherein

R

=

R

L

·

log

2

Q

 and g k is a vector defined by L·log 2 Q rows.

10. The terminal apparatus according to claim 9 , wherein the vector g k is defined by Equation 3 shown below:

g k =[q k·log 2 Q 1 , . . . ,q (k+1)·log 2 Q−1 1 ,q k·log 2 Q 2 , . . . ,q (k+1)·log 2 Q−1 2 , . . . ,q k·log 2 Q L , . . . ,q (k+1)·log 2 Q−1 L ] T ,  <Equation 3>

wherein q j denotes an encoded bit.

Priority Claims (1)
KR 10-2010-0008931 · Feb 1, 2010 · national
Continuity (8)
Continuation 14199865 · Mar 6, 2014
Continuation 13147076
Provisional Application 61149009 · Feb 1, 2009
Provisional Application 61151839 · Feb 11, 2009
Provisional Application 61152271 · Feb 13, 2009
Provisional Application 61152948 · Feb 16, 2009
Provisional Application 61179003 · May 17, 2009
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