Padding for multi-channel memory
Techniques described in the disclosure are generally related to reserving padding bytes in system memory when storing data in the system memory. The reserving of padding bytes may allow a memory interface to efficiently utilize the channels to the system memory when storing or subsequently retrieving the data.
1. A method comprising:
receiving, with a memory interface, a plurality of instructions that instruct the memory interface to store pixel values of a surface in a system memory; and
storing, with the memory interface, the pixel values of the surface, in bits of the system memory other than reserved padding bits in the system memory, in an interleaving manner based on an interleave granularity between at least a first memory unit of the system memory via a first memory controller, and a second, different memory unit of the system memory via a second, different memory controller causing a first set of pixel values of a display tile to be stored within the first memory unit via the first memory controller, and a second set of pixel values of the same display tile to be stored within the second memory unit via the second memory controller, wherein the interleave granularity indicates a number of bits that the memory interface stores in the first memory unit via the first memory controller before storing bits in the second memory unit via the second memory controller, and
wherein storing the pixel values of the surface comprises counting the reserved padding bits as part of the number of bits that are stored in the first memory unit before storing bits in the second memory unit.
2. The method of claim 1 , further comprising:
receiving, with the memory interface, virtual addresses of where the pixel values of the surface are to be stored; and
mapping, with a memory management unit (MMU) the memory interface, the virtual addresses to physical addresses of the bits of the system memory other than the reserved padding bits in the system memory,
wherein storing the pixel values of the surface comprises storing pixel values of the surface, in the bits of the system memory other than the reserved padding bits in the system memory, based on the physical addresses of the bits of the system memory other than the reserved padding bits in the system memory.
3. The method of claim 1 , wherein storing comprises storing the pixel values of the surface, in bits of pages of the system memory, in the interleaving manner.
4. The method of claim 1 , wherein storing comprises storing the pixel values of a line of the surface, in bits of the system memory other than reserved padding bits in the system memory, in the interleaving manner.
5. The method of claim 1 , wherein storing comprises storing the pixel values of a tile of the surface, in bits of the system memory other than reserved padding bits in the system memory, in the interleaving manner.
6. The method of claim 1 , further comprising:
determining a number of the padding bits that cause a number of bits needed to store the first set of pixel values to equal a number of bits needed to store the second set of pixel values; and
reserving the padding bits based on the determined number.
7. The method of claim 1 , further comprising:
reserving, with a first processing unit, the padding bits,
wherein receiving the plurality of instructions comprises receiving the plurality of instructions from a second, different processing unit.
8. The method of claim 7 , wherein the first processing unit comprises a processor, and wherein the second processing unit comprises a graphics processing unit.
9. The method of claim 7 , wherein reserving the padding bits comprises reserving, with a driver executing on the first processing unit, the padding bits.
10. The method of claim 1 , further comprising:
reserving, with a processing unit, the padding bits,
wherein receiving the plurality of instructions comprises receiving the plurality of instructions from the processing unit.
11. The method of claim 10 , wherein the processing unit comprises a graphics processing unit (GPU).
12. The method of claim 1 , wherein the plurality of instructions comprises a first plurality of instructions, the method further comprising:
receiving, with the memory interface, a second plurality of instructions to retrieve the pixel values of the surface from the system memory;
in response to the second plurality of instructions, retrieving, with the memory interface, the first set of pixel values of the display tile from the first memory unit via the first memory controller; and
in response to the second plurality of instructions, at a same time as retrieving the first set of pixel values, retrieving, with the memory interface, the second set of pixel values of the display tile from the second memory unit via the second memory controller.
13. The method of claim 12 , further comprising:
rendering the display tile on a display based on the retrieved first set of pixel values and the second set of pixel values.
14. The method of claim 1 , further comprising:
generating, with a processing unit, the first set of pixel values of the display tile; and
generating, with the processing unit, the second set of pixel values of the display tile.
15. An integrated circuit (IC) comprising:
a first memory controller operatively coupled to a first memory unit of a system memory;
a second, different memory controller operatively coupled to a second, different memory unit of the system memory; and
a memory interface configured to:
receive a plurality of instructions that instruct the memory interface to store pixel values of a surface in the system memory; and
store the pixel values of the surface, in bits of the system memory other than reserved padding bits in the system memory, in an interleaving manner based on an interleave granularity between at least the first memory unit of the system memory via the first memory controller, and the second, different memory unit of the system memory via the second, different memory controller causing a first set of pixel values of a display tile to be stored within the first memory unit via the first memory controller and a second set of pixel values of the same display tile to be stored within the second memory unit via the second memory controller, wherein the interleave granularity indicates a number of bits that the memory interface stores in the first memory unit via the first memory controller before storing bits in the second memory unit via the second memory controller, and
wherein to store the pixel values of the surface, the memory interface is configured to count the reserved padding bits as part of the number of bits that are stored in the first memory unit before storing bits in the second memory unit.
16. The IC of claim 15 , wherein the memory interface comprises a memory management unit (MMU), and wherein the memory interface is configured to:
receive virtual addresses of where the pixel values of the surface are to be stored;
map, with the MMU, the virtual addresses to physical addresses of the bits of the system memory other than the reserved padding bits in the system memory; and
store the pixel values of the surface, in the bits of the system memory other than the reserved padding bits in the system memory, based on the physical addresses of the bits of the system memory other than the reserved padding bits in the system memory.
17. The IC of claim 15 , wherein the memory interface is configured to store the pixel values of the surface, in bits of pages of the system memory, in the interleaving manner.
18. The IC of claim 15 , wherein the memory interface is configured to store the pixel values of a line of the surface, in bits of the system memory other than reserved padding bits in the system memory, in the interleaving manner.
19. The IC of claim 15 , wherein the memory interface is configured to store the pixel values of a tile of the surface, in bits of the system memory other than reserved padding bits in the system memory, in the interleaving manner.
20. The IC of claim 15 , further comprising a processing circuit configured to:
determine a number of the padding bits that cause a number of bits needed to store the first set of pixel values to equal a number of bits needed to store the second set of pixel values; and
reserve the padding bits based on the determined number.
21. The IC of claim 15 , further comprising a first processing circuit and a second, different processing circuit, wherein the first processing circuit is configured to reserve the padding bits, and wherein the memory interface is configured to receive the plurality of instructions from the second processing circuit.
22. The IC of claim 21 , wherein the first processing circuit comprises a processor, and wherein the second processing circuit comprises a graphics processing unit.
23. The IC of claim 21 , wherein the first processing circuit is configured to execute a driver, and reserve the padding bits with the driver.
24. The IC of claim 15 , further comprising a processing circuit configured to reserve the padding bits, and wherein the memory interface receives the plurality of instructions from the processing circuit.
25. The IC of claim 24 , wherein the processing circuit comprises a graphics processing unit.
26. The IC of claim 15 , wherein the plurality of instructions comprises a first plurality of instructions, and wherein the memory interface is configured to:
receive a second plurality of instructions to retrieve the pixel values of the surface from the system memory;
in response to the second plurality of instructions, retrieve the first set of pixel values of the display tile from the first memory unit via the first memory controller; and
in response to the second plurality of instructions, at a same time as retrieving the first set of pixel values, retrieve the second set of pixel values of the display tile from the second memory unit via the second memory controller.
27. The IC of claim 26 , further comprising a processing circuit configured to render the display tile on a display based on the retrieved first set of pixel values and the second set of pixel values.
28. The IC of claim 15 , further comprising a processing circuit configured to:
generate the first set of pixel values of the display tile; and
generate the second set of pixel values of the display tile.
29. A device comprising:
a system memory comprising at least a first memory unit and a second, different memory unit; and
an integrated circuit (IC) comprising:
a first memory controller operatively coupled to the first memory unit of the system memory;
a second, different memory controller operatively coupled to the second, different memory unit of the system memory; and
a memory interface configured to:
receive a plurality of instructions that instruct the memory interface to store pixel values of a surface in the system memory; and
store the pixel values of the surface, in bits of the system memory other than reserved padding bits in the system memory, in an interleaving manner based on an interleave granularity between at least the first memory unit of the system memory via the first memory controller, and the second, different memory unit of the system memory via the second, different memory controller causing a first set of pixel values of a display tile to be stored within the first memory unit via the first memory controller and a second set of pixel values of the same display tile to be stored within the second memory unit via the second memory controller, wherein the interleave granularity indicates a number of bits that the memory interface stores in the first memory unit via the first memory controller before storing bits in the second memory unit via the second memory controller, and
wherein to store the pixel values of the surface, the memory interface is configured to count the reserved padding bits as part of the number of bits that the memory interface stores in the first memory unit before storing bits in the second memory unit.
30. The device of claim 29 , wherein the memory interface comprises a memory management unit (MMU), and wherein the memory interface is configured to:
receive virtual addresses of where the pixel values of the surface are to be stored;
map, with the MMU, the virtual addresses to physical addresses of the bits of the system memory other than the reserved padding bits in the system memory; and
store the pixel values of the surface, in the bits of the system memory other than the reserved padding bits in the system memory, based on the physical addresses of the bits of the system memory other than the reserved padding bits in the system memory.
31. The device of claim 29 , further comprising a processing unit configured to:
determine a number of the padding bits that cause a number of bits needed to store the first set of pixel values to equal a number of bits needed to store the second set of pixel values; and
reserve the padding bits based on the determined number.
32. The device of claim 29 , wherein the IC includes the processing unit.
33. The device of claim 29 , wherein the plurality of instructions comprises a first plurality of instructions, and wherein the memory interface is configured to:
receive a second plurality of instructions to retrieve the pixel values of the surface from the system memory;
in response to the second plurality of instructions, retrieve the first set of pixel values of the display tile from the first memory unit via the first memory controller; and
in response to the second plurality of instructions, at a same time as retrieving the first set of pixel values, retrieve the second set of pixel values of the display tile from the second memory unit via the second memory controller.
34. The device of claim 33 , further comprising:
a display; and
a processing unit configured to render the display tile on the display based on the retrieved first set of pixel values and the second set of pixel values.
35. A device comprising:
a system memory comprising at least a first memory unit and a second, different memory unit; and
an integrated circuit (IC) comprising:
a first memory controller operatively coupled to the first memory unit of the system memory;
a second, different memory controller operatively coupled to the second, different memory unit of the system memory; and
means for receiving a plurality of instructions that instruct the memory interface to store pixel values of a surface in a system memory; and
means for storing the pixel values of a surface, in bits of the system memory other than reserved padding bits in the system memory, in an interleaving manner based on an interleave granularity between at least a first memory unit of the system memory via a first memory controller, and a second, different memory unit of the system memory via a second, different memory controller causing a first set of pixel values of a display tile to be stored within the first memory unit via the first memory controller and a second set of pixel values of the same display tile to be stored within the second memory unit via the second memory controller, wherein the interleave granularity indicates a number of bits that the memory interface stores in the first memory unit via the first memory controller before storing bits in the second memory unit via the second memory controller, and
wherein the means for storing the pixel values of the surface comprises means for counting the reserved padding bits as part of the number of bits that the memory interface stores in the first memory unit before storing bits in the second memory unit.
36. A non-transitory computer-readable storage medium having stored thereon instructions that upon execution cause one or more processors to:
instruct a memory interface to store pixel values of a surface, in bits of a system memory other than reserved padding bits in the system memory, in an interleaving manner based on an interleave granularity between at least a first memory unit of the system memory via a first memory controller, and a second, different memory unit of the system memory via a second, different memory controller causing a first set of pixel values of a display tile to be stored within the first memory unit via the first memory controller and a second set of pixel values of the same display tile to be stored within the second memory unit via the second memory controller, wherein the interleave granularity indicates a number of bits that the memory interface stores in the first memory unit via the first memory controller before storing bits in the second memory unit via the second memory controller, and wherein the instructions that cause the one or more processors to store the pixel values of the surface comprise instructions that cause the one or more processors to count the reserved padding bits as part of the number of bits that are stored in the first memory unit before storing bits in the second memory unit.