Semiconductor devices including multilayer source/drain stressors and methods of manufacturing the same
A semiconductor device including source drain stressors and methods of manufacturing the same are provided. The methods may include forming a recess region in the substrate at a side of a gate pattern, and an inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes. The method may further include performing a first selective epitaxial growth (SEG) process to form a base epitaxial pattern on the inner surface of the recess region at a process pressure in a range of about 50 Torr to about 300 Torr. The method may also include performing a second selective epitaxial growth (SEG) process to form a bulk epitaxial pattern on the base epitaxial pattern.
1. A semiconductor device comprising:
a substrate comprising a first semiconductor element;
a gate pattern on the substrate;
a base epitaxial pattern on an inner surface of a recess region in the substrate at a side of the gate pattern, the inner surface of the recess region including a first surface defining a bottom surface of the recess region and a second surface defining a sidewall surface of the recess region, and the base epitaxial pattern comprising a second semiconductor element different from the first semiconductor element;
a bulk epitaxial pattern on the base epitaxial pattern, the bulk epitaxial pattern comprising the second semiconductor element; and
a buffer epitaxial pattern between the base epitaxial pattern and the bulk epitaxial pattern, the buffer epitaxial pattern comprising the second semiconductor element,
wherein the base epitaxial pattern has a first thickness on the first surface and a second thickness on the second surface, wherein the buffer epitaxial pattern has a third thickness on the first surface and a fourth thickness on the second surface, and wherein a ratio of the fourth thickness to the third thickness of the buffer epitaxial pattern is less than a ratio of the second thickness to the first thickness of the base epitaxial pattern.
2. The semiconductor device of claim 1 , wherein the first surface is a (100) crystal plane, and wherein the second surface is one of {111} crystal planes.
3. The semiconductor device of claim 2 , wherein the ratio of the second thickness to the first thickness of the base epitaxial pattern is in a range of about ¾ to about 1.
4. The semiconductor device of claim 1 , wherein the substrate comprises first dopants of a first conductivity type and the bulk epitaxial pattern comprises second dopants of a second conductivity type that is different from the first conductivity, and wherein the base epitaxial pattern is free of the second dopants.
5. The semiconductor device of claim 1 , wherein the base epitaxial pattern is formed at a process pressure in a range of about 50 Torr to about 300 Torr.
6. The semiconductor device of claim 1 , wherein the recess region comprises an undercut region tapered toward a region under the gate pattern.
7. The semiconductor device of claim 1 , wherein a second semiconductor element concentration in the buffer epitaxial pattern is less than a second semiconductor element concentration in the bulk epitaxial pattern and is greater than a second semiconductor element concentration in the base epitaxial pattern.
8. The semiconductor device of claim 7 , wherein the substrate comprises first dopants of a first conductivity type, the bulk epitaxial pattern and the buffer epitaxial pattern comprise second dopants of a second conductivity type different from the first conductivity type, wherein a second dopant concentration in the buffer epitaxial pattern is less than a second dopant concentration in the bulk epitaxial pattern, and wherein the base epitaxial pattern is free of the second dopants or a second dopant concentration in the base epitaxial pattern is less than the second dopant concentration in the buffer epitaxial pattern.