Vertical transistor devices for embedded memory and logic technologies

1. A vertical transistor device, comprising:

an epitaxial source semiconductor region disposed on a substrate;

an epitaxial channel semiconductor region disposed on the source semiconductor region;

an epitaxial drain semiconductor region disposed on the channel semiconductor region; and

a gate electrode region surrounding a plurality of sidewalls of the semiconductor channel region, wherein a composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate.

2. The vertical transistor device of claim 1 , wherein the source semiconductor region has a higher effective mass than that of the channel and drain semiconductor regions.

3. The vertical transistor device of claim 2 , wherein the effective mass of the source semiconductor region is approximately twice an effective mass of the channel and drain semiconductor regions.

4. The vertical transistor device of claim 1 , wherein the channel semiconductor region has a compositional variation between a first interface with the source semiconductor region and a second interface with the drain semiconductor region.

5. The vertical transistor device of claim 4 , wherein the compositional variation further comprises a grading of the channel semiconductor region throughout the epitaxial film thickness.

6. The vertical transistor device of claim 4 , wherein the channel semiconductor region comprises a SiGe alloy, and wherein the Ge content is higher at the first interface than at the second interface, or wherein the channel semiconductor comprises a In alloy, and wherein the In content is higher at the first interface than at the second interface.

7. The vertical transistor device of claim 1 , wherein the channel semiconductor is silicon or a SiGe alloy, and wherein the high mobility injection region is disposed on the source semiconductor region and is composed of Ge.

8. The vertical transistor device of claim 7 , wherein the compositional variation further comprises a grading of the channel semiconductor region from the high mobility injection region to the second interface.

9. The vertical transistor device of claim 1 , wherein the channel semiconductor region is a different semiconductor material in comparison to the source and drain semiconductor regions.

10. A vertical transistor device, comprising:

an epitaxial source semiconductor region disposed on a substrate;

an epitaxial channel semiconductor region disposed on the source semiconductor region;

an epitaxial drain semiconductor region disposed on the channel semiconductor region; and

a gate electrode region surrounding a plurality of sidewalls of the semiconductor channel region, wherein a composition of the gate electrode region varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate.

11. The vertical transistor device of claim 10 , wherein a composition of the gate electrode in contact with the gate dielectric varies along the longitudinal axis to differentiate a work function from a first level proximate to the source semiconductor region to a second level proximate to the drain semiconductor region.

12. The vertical transistor device of claim 11 , wherein the gate electrode composition is graded from a first alloy composition proximate to the source semiconductor region to a second alloy composition proximate to the drain semiconductor region.

13. The vertical transistor device of claim 11 , wherein the channel semiconductor region has a compositional variation between a first interface with the source semiconductor region and a second interface with the drain semiconductor region, a semiconductor compositional variation to magnify a difference in transistor threshold voltage associated with a differentiation in the gate electrode work function.

14. The vertical transistor device of claim 10 , wherein a work function of the gate electrode is greater proximate to the drain semiconductor region than proximate to the source semiconductor region.

15. A computing device, comprising:

memory to store electronic data; and

a processor coupled to the memory, the processor to process electronic data, the processor includes an integrated circuit die having a plurality of vertical transistor devices, at least one vertical transistor device comprising:

a first epitaxial semiconductor region disposed on a substrate;

a second epitaxial semiconductor region disposed on the first semiconductor region;

a third epitaxial semiconductor region disposed on the second semiconductor region; and

a gate electrode region surrounding a plurality of sidewalls of the second semiconductor region, wherein a composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate.

16. The computing device of claim 15 , wherein the first semiconductor region has a higher effective mass than that of the second and third semiconductor regions.

17. The computing device of claim 15 , wherein the first semiconductor region is a source region, the second semiconductor region is a channel region, and the third semiconductor region is a drain region, wherein the channel semiconductor region has a compositional variation between a first interface with the source semiconductor region and a second interface with the drain semiconductor region.

18. The computing device of claim 17 , wherein the compositional variation further comprises a grading of the channel semiconductor region throughout the epitaxial film thickness.

19. The computing device of claim 15 , wherein the first semiconductor region is a drain region, the second semiconductor region is a channel region, and the third semiconductor region is a source region.