Schmitt trigger in FDSOI technology

1. An integrated circuit die:

a first inverter including;

a first transistor having a first gate, a second gate, a channel region, a source, and a drain;

a second transistor having a first gate, a second gate, a channel region, a source, and a drain coupled to the drain of the first transistor;

an input coupled to the first gates of the first and second transistors; and

an output coupled to drain terminals of the first and second transistors;

a second inverter including:

an input coupled to the output of the first inverter; and

an output coupled configured to supply an output signal to the second gates of the first and second transistors;

an insulator layer;

a first semiconductor substrate on the insulator layer, the channel regions, the sources, and the drains of the first and second transistors being positioned in the first semiconductor substrate;

a gate dielectric on the first semiconductor substrate, the first gates of the first and second transistors being separated from the first semiconductor substrate by the gate dielectric; and

a second semiconductor substrate separated from the first semiconductor substrate by the insulator layer, the second gates of the first and second transistors being positioned in the first semiconductor substrate and separated from the respective channel regions by the insulator layer.

2. The integrated circuit die of claim 1 comprising:

a via in the insulator layer; and

a conductive material in the via electrically connecting the second gate of the first transistor to the output of the second inverter.

3. The integrated circuit die of claim 1 comprising a third transistor having a drain terminal coupled to the source of the first transistor, a gate coupled to the input, and a source coupled to a high supply voltage.

4. The integrated circuit die of claim 3 comprising a fourth transistor having a drain terminal coupled to the source of the second transistor, a gate coupled to the input, and a source coupled to a low supply voltage.

5. The integrated circuit die of claim 4 wherein the first and third transistors are PMOS transistors.

6. The integrated circuit die of claim 5 wherein the second and fourth transistors are NMOS transistors.

7. The integrated circuit die of claim 6 wherein a channel region width to length ratio of the fourth transistor is greater than a channel region width to length ratio of the second transistor.

8. The integrated circuit die of claim 7 wherein a channel width to length ratio of the third transistor is greater than a channel width to length ratio of the first transistor.

9. The integrated circuit die of claim 8 wherein the first and second inverters comprise a Schmitt trigger, the input of the first inverter being the input of the Schmitt trigger, the output of the second inverter being the output of the Schmitt trigger, a High threshold voltage of the Schmitt trigger based in part on a difference between the channel region width to length ratios of the second and fourth transistors, a Low threshold voltage of the Schmitt trigger based in part on a difference between the width to length ratios of the first and third transistors.

10. A Schmitt trigger comprising:

an input stage including a first and a second transistor each having first gate configured to receive an input voltage and each having a second gate, the input stage configured to output a first output signal on a drain terminal of the first transistor;

an output stage coupled to the input stage and configured to receive the first output signal and to output a second output signal having a high logic value when the input voltage transitions from below a low threshold voltage to above a high threshold voltage and having a low logic value when the input voltage transitions from above the high threshold voltage to below the low threshold voltage, the second gates each receiving the second output voltage;

an insulator layer;

a first semiconductor substrate on the insulator layer, each of the first and second transistors including a channel region, a source, and a drain positioned in the first semiconductor substrate;

a gate dielectric on the first semiconductor substrate, the first gates of the first and second transistors being separated from the first semiconductor substrate by the gate dielectric; and

a second semiconductor substrate separated from the first semiconductor substrate by the insulator layer, the second gates of the first and second transistors being positioned in the first semiconductor substrate and separated from the respective channel regions by the insulator layer.

11. The Schmitt trigger of claim 10 wherein the input stage is a first inverter.

12. The Schmitt trigger of claim 11 wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor, the drain terminal of the first transistor being connected to a drain terminal of the second transistor.

13. The Schmitt trigger of claim 12 comprising a third transistor having a gate configured to receive the input voltage, a source configured to receive a high supply voltage, and a drain coupled to a source of the first transistor.

14. The Schmitt trigger of claim 13 comprising a fourth transistor having a gate configured to receive the input voltage, a source configured to receive a low supply voltage, and a drain coupled to the source of the first transistor.

15. A method comprising:

supplying an input voltage to a first gate terminal of a first transistor and to a first gate terminal of a second transistor, each of the first and second transistors having a channel region, a source, and a drain positioned in a first semiconductor substrate, and each of the first and second transistors having a first gate separated from the first semiconductor substrate by a gate dielectric on the first semiconductor substrate;

outputting a first output voltage from a drain terminal of the first transistor;

supplying the first output voltage to an inverter;

generating a second output voltage at an output of the inverter; and

supplying the second output voltage to a second gate terminal of the first transistor and a second gate terminal of the second transistor, each of the first and second transistors having a second gate positioned in the first semiconductor substrate and separated from the respective channel region by an insulator layer on which the first semiconductor substrate is disposed, the insulator layer separating the first semiconductor substrate from a second semiconductor substrate.

16. The method of claim 15 comprising generating the second output voltage at a high logic level when the input voltage transitions from below a low threshold value to above a high threshold voltage, the high threshold value being greater than the low threshold value and lower than the high logic level.

17. The method of claim 16 comprising generating the second output voltage at a low logic level when the input voltage transitions from above the high threshold value to below the low threshold voltage, the low threshold value being greater than the low logic level.

18. The method of claim 17 comprising:

supplying the input voltage to a gate of a third transistor having a drain coupled to the source of the first transistor; and

supplying the input voltage to a gate of a fourth transistor having a drain coupled to the source of the second transistor.