Multi-channel transceiver

1. A multi-channel transceiver, comprising:

a phase-locked loop circuit for generating a first clock signal set and a second clock signal set, wherein the first clock signal set and the second clock signal set have different frequencies;

a first transmitting channel comprising a first phase adjusting circuit and a first transmitter, wherein the first phase adjusting circuit receives the first clock signal set and generates a first spread spectrum clock signal with a first spread spectrum clock generator profile, wherein according to the first spread spectrum clock signal, the first transmitter generates a first serial data, and the first transmitter comprises a serializer for converting a parallel data into the first serial data; and

a second transmitting channel comprising a second phase adjusting circuit and a second transmitter, wherein the second phase adjusting circuit receives the second clock signal set and generates a second spread spectrum clock signal with a second spread spectrum clock generator profile, wherein according to the second spread spectrum clock signal, the second transmitter generates a second serial data.

2. The multi-channel transceiver as claimed in claim 1 , further comprising:

a first receiving channel comprising a first receiver and a first clock and data recovery circuit, wherein a third serial data is received by the first receiver and transmitted to the first clock and data recovery circuit, and a first sampling clock is generated by the first clock and data recovery circuit according to a first specified clock signal of the first clock signal set, wherein the third serial data is sampled according to the first sampling clock; and

a second receiving channel comprising a second receiver and a second clock and data recovery circuit, wherein a fourth serial data is received by the second receiver and transmitted to the second clock and data recovery circuit, and a second sampling clock is generated by the second clock and data recovery circuit according to a second specified clock signal of the second clock signal set, wherein the fourth serial data is sampled according to the second sampling clock.

3. The multi-channel transceiver as claimed in claim 1 , wherein the first phase adjusting circuit comprises:

a first controlling circuit for generating a first control signal; and

a first phase interpolator for selecting the first clock signal set according to the first control signal, thereby generating the first spread spectrum clock signal.

4. The multi-channel transceiver as claimed in claim 3 , wherein the first clock signal set contains four 90-degree phase-shifted clock signals, the first control signal has n bits, and the first phase interpolator comprises:

a selector for receiving the 90-degree phase-shifted clock signals and selectively generating a first selected clock signal and a second selected clock signal according to two bits of the first control signal;

a weighting controller for adjusting a weighting parameter according to other (n−2) bits of the first control signal, wherein the weighting controller multiples the first selected clock signal by the weighting parameter to generate a first weighted clock signal, and the weighting controller multiples the second selected clock signal by a difference between 1 and the weighting parameter to generate a second weighted clock signal, wherein the weighting parameter is larger than or equal to 0 and smaller than or equal to 1; and

a combiner for combining the first weighted clock signal and the second weighted clock signal, thereby generating the first spread spectrum clock signal.

5. The multi-channel transceiver as claimed in claim 4 , wherein a spread spectrum clocking frequency deviation is obtained according to an increment value, a decrement value or a changing rate of the first control signal, and the first spread spectrum clock generator profile is determined according to the spread spectrum clocking frequency deviation.

6. The multi-channel transceiver as claimed in claim 1 , wherein the second phase adjusting circuit comprises:

a second controlling circuit for generating a second control signal; and

a second phase interpolator for selecting the second clock signal set according to the second control signal, thereby generating the second spread spectrum clock signal.

7. A multi-channel transceiver, comprising:

a phase-locked loop circuit for generating a first clock signal set and a second clock signal set, wherein the first clock signal set and the second clock signal set have different frequencies;

a first transmitting channel comprising a first phase adjusting circuit and a first transmitter, wherein the first phase adjusting circuit receives the first clock signal set and generates a first spread spectrum clock signal with a first spread spectrum clock generator profile, wherein according to the first spread spectrum clock signal, the first transmitter generates a first serial data;

a second transmitting channel comprising a second phase adjusting circuit and a second transmitter, wherein the second phase adjusting circuit receives the second clock signal set and generates a second spread spectrum clock signal with a second spread spectrum clock generator profile, wherein according to the second spread spectrum clock signal, the second transmitter generates a second serial data;

a first receiving channel comprising a first receiver and a first clock and data recovery circuit, wherein a third serial data is received by the first receiver and transmitted to the first clock and data recovery circuit, and a first sampling clock is generated by the first clock and data recovery circuit according to a first specified clock signal of the first clock signal set, wherein the third serial data is sampled according to the first sampling clock; and

a second receiving channel comprising a second receiver and a second clock and data recovery circuit, wherein a fourth serial data is received by the second receiver and transmitted to the second clock and data recovery circuit, and a second sampling clock is generated by the second clock and data recovery circuit according to a second specified clock signal of the second clock signal set, wherein the fourth serial data is sampled according to the second sampling clock.

8. The multi-channel transceiver as claimed in claim 7 , wherein the first phase adjusting circuit comprises:

a first controlling circuit for generating a first control signal; and

a first phase interpolator for selecting the first clock signal set according to the first control signal, thereby generating the first spread spectrum clock signal.

9. The multi-channel transceiver as claimed in claim 8 , wherein the first clock signal set contains four 90-degree phase-shifted clock signals, the first control signal has n bits, and the first phase interpolator comprises:

a selector for receiving the 90-degree phase-shifted clock signals and selectively generating a first selected clock signal and a second selected clock signal according to two bits of the first control signal;

a weighting controller for adjusting a weighting parameter according to other (n−2) bits of the first control signal, wherein the weighting controller multiples the first selected clock signal by the weighting parameter to generate a first weighted clock signal, and the weighting controller multiples the second selected clock signal by a difference between 1 and the weighting parameter to generate a second weighted clock signal, wherein the weighting parameter is larger than or equal to 0 and smaller than or equal to 1; and

a combiner for combining the first weighted clock signal and the second weighted clock signal, thereby generating the first spread spectrum clock signal.

10. The multi-channel transceiver as claimed in claim 9 , wherein a spread spectrum clocking frequency deviation is obtained according to an increment value, a decrement value or a changing rate of the first control signal, and the first spread spectrum clock generator profile is determined according to the spread spectrum clocking frequency deviation.

11. The multi-channel transceiver as claimed in claim 7 , wherein the second phase adjusting circuit comprises:

a second controlling circuit for generating a second control signal; and

a second phase interpolator for selecting the second clock signal set according to the second control signal, thereby generating the second spread spectrum clock signal.

12. The multi-channel transceiver as claimed in claim 7 , wherein the first transmitter comprises a serializer for converting a parallel data into the first serial data.