Semiconductor device and method for manufacturing the same
In one embodiment, a semiconductor device includes a first diffusion layer of a first conductive type and a second diffusion layer of a second conductive type which is a reverse conductive type of the first conductive type, the first conductive type first diffusion layer and the second conductive type diffusion layer being spaced apart and provided in a semiconductor layer, a pocket region of the second conductive type which is provided on a surface portion of the semiconductor layer adjacently to the first diffusion layer, and a first extension region of the first conductive type which is provided in the semiconductor layer to cover at least a portion of the pocket region. A second diffusion layer side end portion of the first extension region is positioned closer to a second diffusion layer side than a second diffusion layer side end portion of the pocket region.
1. A semiconductor device comprising:
a first diffusion layer of a first conductive type and a second diffusion layer of a second conductive type which is a reverse conductive type of the first conductive type, the first conductive type first diffusion layer and the second conductive type second diffusion layer being spaced apart and provided in a semiconductor layer;
a gate insulation film which is provided on the semiconductor layer between the first diffusion layer and the second diffusion layer;
a gate electrode which is provided on the gate insulation film;
a pocket region of the second conductive type which is provided on a surface portion of the semiconductor layer adjacently to the first diffusion layer; and
a first extension region of the first conductive type which is provided in the semiconductor layer to cover at least a portion of the pocket region,
wherein a second diffusion layer side end portion of the first extension region is positioned closer to a second diffusion layer side than a second diffusion layer side end portion of the pocket region, and
wherein one of the first and second diffusion layers is a source, and the other of the first and second diffusion layers is a drain.
2. The semiconductor device according to claim 1 , wherein the first extension region is in contact with the first diffusion layer.
3. The semiconductor device according to claim 2 , wherein the first diffusion layer of the first conductive type is a P type source region and the second diffusion layer of the second conductive type is an N type drain region.
4. The semiconductor device according to claim 1 , further comprising a second extension region of the first conductive type which is provided on the surface portion of the semiconductor layer adjacently to the first diffusion layer,
wherein a second diffusion layer side end portion of the second extension region is positioned closer to a first diffusion layer side than the second diffusion layer side end portion of the pocket region.
5. The semiconductor device according to claim 4 , wherein an impurity concentration of the second extension region is higher than an impurity concentration of the first extension region.
6. The semiconductor device according to claim 5 , wherein the first extension region is in contact with the first diffusion layer.
7. The semiconductor device according to claim 6 , wherein the first diffusion layer of the first conductive type is a P type source region, and the second diffusion layer of the second conductive type is an N type drain region.
8. The semiconductor device according to claim 1 , wherein the pocket region is provided between the first diffusion layer and the first extension region, and the first extension region is provided spaced apart from the first diffusion layer.
9. The semiconductor device according to claim 1 , wherein the first diffusion layer of the first conductive type is a P type source region, and the second diffusion layer of the second conductive type is an N type drain region.
10. The semiconductor device according to claim 1 , wherein a first diffusion layer side end portion of the pocket region intervenes between the surface portion of the semiconductor layer and a first diffusion layer side end portion of the first extension region.