IP Library Granted Patent US 9,325,614
Granted Patent B2
US 9,325,614 · App. 14/197,414 · Granted Apr 26, 2016

Methods and systems for detecting a preamble of a data packet in wireless communication systems

Inventors: Sarad Ammanat Venugopalan (Kerala, IN); Srikanth Subramanian (Chennai, IN)
Assignees: KBC RESEARCH FOUNDATION PVT. LTD.; ANNA UNIVERSITY
H04L45/74H04L65/1069H04L69/22H04W56/002H04W40/248
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Quick Facts
Patent No.
US 9,325,614
App. No.
14/197,414
Granted
Apr 26, 2016
Kind
B2
Abstract

Methods and systems for detecting a preamble of a data packet in wireless communication systems is provided. To determine a preamble from a received signal, which may include a noise-altered preamble bit sequence, linear feedback shift registers (LFSRs) can be used to generate a count of the received preamble, and the count is compared to pre-generated scores to identify a match. Example methods include for each of a number of different preamble orientations of a preamble, generating a count value based on a comparison of bits of the preamble with a random bit sequence to produce a sequence of count values, and comparing the sequence of count values with m sequences of count values. A sequence of count values is identified that includes a maximum number of matching elements, and the received preamble is determined to be one of the m preambles corresponding to the identified sequence.

Claims (65)

1. A receiver comprising:

a preamble processor including a register, a first comparator, and a counter, the preamble processor configured to receive a preamble and, for each of a number of different preamble orientations n of the preamble, generate a (1×n) matrix of count values output by the counter based on a comparison by the first comparator of each bit of the preamble with a random bit sequence output by the register;

a look-up table; and

a second comparator configured to identify a row of an (m×n) matrix, constructed of a plurality number of preambles m and preamble orientations n thereof, retrieved from the look-up table that best matches the (1×n) matrix, and provide the identified row to the preamble processor;

wherein m and n are integer values greater than zero; and

wherein the preamble processor is further configured to identify one of the number of preambles m corresponding to the identified row as the received preamble.

2. The receiver of claim 1 , wherein the first comparator is configured to generate an output to the counter for each comparison in which a bit of the preamble and the random bit sequence do not match, and to read a subsequent bit of the preamble each time the bit of the preamble and the random bit sequence match.

3. The receiver of claim 2 , wherein the counter is configured to increment a count value of the count values for each output of the first comparator, and to maintain the count values as measures of the matches.

4. A receiver comprising:

a preamble processor having a first comparator, the preamble processor configured to receive a preamble and, for each of a number of different preamble orientations n of the preamble, generate a (1×n) matrix of values based on a comparison by the first comparator of each bit of the preamble with a random bit sequence; and

a second comparator configured to identify a row of an (m×n) matrix, constructed of a plurality number of preambles m and the n preamble orientations of the m preambles, that best matches the (1×n) matrix, and to provide the identified row to the preamble processor;

wherein m and n are integer values greater than zero; and

wherein the preamble processor is further configured to identify the received preamble as one of the number of preambles m corresponding to the identified row.

5. The receiver of claim 4 , further comprising:

a counter;

wherein the preamble processor further includes a linear feedback shift register (LFSR);

wherein the counter is operatively coupled to the first comparator and configured to maintain a count value indicating matches of the preamble bits with output bits of the LFSR;

wherein for every bit of the preamble compared by the first comparator, the counter increments the count value;

wherein the counter is configured to further increment the count value each time a bit of the random bit sequence output by the LFSR does not match the bit read from the preamble;

wherein the counter is configured to produce a sequence of the count values corresponding to each one of the n preamble orientations; and

wherein the preamble processor is further configured to identify the received preamble as the one of the number of preambles m corresponding to the identified row based on a count value sequence having the greatest number of values that match values of a sequence of count values produced by the counter.

6. The receiver of claim 4 , further comprising:

a look-up table;

wherein the second comparator is configured to retrieve the (m×n) matrix from the look-up table.

7. A wireless communication system, comprising:

a plurality of base stations; and

a receiver including:

a preamble processor including a register, a first comparator, and a counter, the preamble processor configured to receive a preamble from one base station of the plurality of base stations and, for each of a number of different preamble orientations n of the preamble, generate a (1×n) matrix of count values output by the counter based on a comparison by the first comparator of each bit of the preamble with a random bit sequence output by the register;

a look-up table; and

a second comparator configured to identify a row of an (m×n) matrix, constructed of a number of preambles m and preamble orientations n thereof, retrieved from the look-up table that best matches the (1×n) matrix, and provide the identified row to the preamble processor;

wherein m and n are integer values greater than zero; and

wherein the preamble processor is further configured to identify one of the number of preambles m corresponding to the identified row as the received preamble.

8. The wireless communication system of claim 7 , wherein the one base station is configured to communicate using a preamble of the number of preambles that is different from preambles used by the other base stations of the plurality of base stations in the wireless communication system.

9. The wireless communication system of claim 7 , wherein the first comparator is configured to generate an output to the counter for each comparison in which a bit of the preamble and the random bit sequence do not match, and to read a subsequent bit of the preamble each time the bit of the preamble and the random bit sequence match.

10. The wireless communication system of claim 7 , wherein the counter is configured to increment a count value of the count values for each output of the first comparator, and to maintain the count values as measures of the matches.

11. A method of communicating in a wireless communication system including a plurality of receivers configured to communicate via a plurality of base stations, the method comprising:

at one of the plurality of base stations:

generating an (m×n) matrix, wherein m is a number of preambles for data packets in the wireless communication system and n is a number of preamble orientations of each of the m preambles; and

providing the (m×n) matrix to each of the plurality of receivers; and

at one of the plurality of receivers:

receiving one of the m preambles from one of the plurality of base stations and, for each of the preamble orientations n of the received preamble, generating, by a preamble processor, a (1×n) matrix of values based on a comparison of each bit of the preamble with bits of a random bit sequence;

identifying a row of the (m×n) matrix that best matches the (1×n) matrix; and

identifying, by the preamble processor, one of the number of preambles m corresponding to the identified row as the received preamble;

wherein m and n are integer values greater than zero.

12. The method of claim 11 , further comprising:

by the preamble processor, generating the random bit sequence.

13. The method of claim 11 , further comprising:

by the preamble processor, generating an output for each comparison in which a bit of the preamble and a bit of the random bit sequence do not match; and

reading a subsequent bit of the preamble each time the bit of the preamble and a bit of the random bit sequence match.

14. The method of claim 13 , further comprising:

by the preamble processor:

incrementing a value of the values of the (1×n) matrix for each bit comparison; and

maintaining the values as measures of matches of the bit comparisons.

15. The method of claim 11 , further comprising:

by the preamble processor, comparing the each bit of the preamble with the random bit sequence.

16. The method of claim 11 ,

wherein the identifying of a row of the (m×n) matrix that best matches the (1×n) matrix is performed by a comparator of the receiver; and

wherein the method further comprises providing, by the comparator, the identified row of the (m×n) matrix that best matches the (1×n) matrix.

17. The method of claim 16 , further comprising:

by the comparator, generating an output for each comparison in which a bit of the preamble and a bit of the random bit sequence do not match; and

reading a subsequent bit of the preamble each time the bit of the preamble and a bit of the random bit sequence match.

18. The method of claim 17 , further comprising:

by the preamble processor:

incrementing a value of the values of the (1×n) matrix for each bit comparison; and

maintaining the values as measures of matches of the bit comparisons.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS, RECORDED ON JANUARY 29, 2019 AT REEL 048373 FRAME 0217 Recorded Sep 22, 2025
From: CRESTLINE DIRECT FINANCE, L.P., AS COLLATERAL AGENT
To: EMPIRE TECHNOLOGY DEVELOPMENT LLC
Reel/Frame 072936/0464 →
RELEASE OF SECURITY INTEREST Recorded Jul 31, 2019
From: CRESTLINE DIRECT FINANCE, L.P.
To: EMPIRE TECHNOLOGY DEVELOPMENT LLC
Reel/Frame 049924/0794 →
SECURITY INTEREST Recorded Jan 29, 2019
From: EMPIRE TECHNOLOGY DEVELOPMENT LLC
To: CRESTLINE DIRECT FINANCE, L.P.
Reel/Frame 048373/0217 →
Continuity (2)
Continuation 12716803 · Mar 3, 2010
Related Publication 20140185631A1 · Jul 3, 2014