Conformal low temperature hermetic dielectric diffusion barriers
Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.
1. A microelectronic device, comprising:
a pair of adjacent metal interconnect lines disposed over a substrate, the pair of interconnect lines separated by a space;
a low-k interlayer dielectric (ILD) material disposed in the space between the metal interconnect lines;
an air gap disposed within the ILD material; and
a contiguous dielectric diffusion barrier that is a multi-layered film stack spanning the space, the multi-layered film stack comprising a first material layer on a second material layer between the air gap and a portion of the low-k ILD material on a sidewall of at least one of the metal interconnect lines, wherein one of the first material layer and the second material layer comprises a metal species and oxygen.
2. The microelectronic device of claim 1 , wherein one of the first material layer and the second material layer comprises a metal silicate.
3. The microelectronic device of claim 2 , wherein the metal silicate comprises oxygen and silicon and one of aluminum or magnesium.
4. The microelectronic device of claim 1 , wherein one of the first material layer and the second material layer comprises a layer of high-k dielectric material having a dielectric constant of at least 10.
5. The microelectronic device of claim 4 , wherein the layer of high-k dielectric material has a thickness below 8 nm.
6. The microelectronic device of claim 4 , wherein the layer of high-k dielectric material comprises at least one of Al 2 O 3 , MgO 2 , and HfO 2 .
7. The microelectronic device of claim 6 , wherein the layer of high-k dielectric material consists essentially of one of: Al 2 O 3 , MgO 2 , and HfO 2 .
8. The microelectronic device of claim 4 , wherein other one of the first material layer and the second material layer is a layer of intermediate-k dielectric material having the dielectric constant smaller than that of the layer of the high-k dielectric material and higher than that of the low-k interlayer dielectric material.
9. The microelectronic device of claim 8 , wherein the thickness of dielectric diffusion barrier is less than 10 nm.
10. The microelectronic device of claim 8 , wherein the intermediate-k dielectric material comprises carbon-doped silicon oxynitride (SiON(C):H) and has a thickness less than 4 nm.