Multi-threshold voltage FETs

1. An integrated circuit device comprising:

a first transistor including a first strained channel region, the first strained channel region disposed between first source/drain regions, the first source/drain regions formed from a first III-V semiconductor material; and

a second transistor including a second strained channel region, the first strained channel region and the second strained channel region being subjected to opposite strains, the second strained channel region disposed between second source/drain regions, the second source/drain regions formed from a second III-V semiconductor material, the first III-V semiconductor material and the second III-V semiconductor material being a same material with different stoichiometric ratios, wherein the first strained channel region and the second strained channel region comprises a same III-V semiconductor material having a same stoichiometric ratio, and wherein the first transistor and the second transistor are each an n-type field effect transistor (FET).

2. The integrated circuit device of claim 1 , wherein the n-type field effect transistor is one of a fin field effect transistor (FinFET) and a quantum well field effect transistor (QWFET).

3. The integrated circuit device of claim 1 , wherein the first III-V semiconductor material and the second III-V semiconductor material is indium gallium arsenide.

4. The integrated circuit device of claim 1 , further comprising a first buffer underlying the first strained channel region and a second buffer underlying the second strained channel region.

5. The integrated circuit device of claim 4 , wherein the first buffer is disposed on a first template and the second buffer is disposed on a second template, each of the first template and the second template comprising indium phosphorous.

6. The integrated circuit device of claim 4 , wherein the first buffer and the second buffer are formed of a same material.

7. The integrated circuit device of claim 6 , wherein the first buffer and the second buffer is formed of indium aluminum arsenide.

8. The integrated circuit device of claim 1 , wherein the first strained channel region and the second strained channel region is formed of a third III-V semiconductor material, the first III-V semiconductor material and the third III-V semiconductor material being a same material with different stoichiometric ratios.

9. The integrated circuit device of claim 8 , wherein the first III-V semiconductor material, the second III-V semiconductor material, and the third III-V semiconductor material is indium gallium arsenide, the first III-V semiconductor material having a lower concentration of indium than the third III-V semiconductor material, the second III-V semiconductor material having a higher concentration of indium than the third III-V semiconductor material.

10. The integrated circuit device of claim 8 , wherein the first III-V semiconductor material, the second III-V semiconductor material, and the third III-V semiconductor material is indium gallium antimonide, the first III-V semiconductor material having a lower concentration of indium than the third III-V semiconductor material, the second III-V semiconductor material having a higher concentration of indium than the third III-V semiconductor material.

11. The integrated circuit device of claim 1 , wherein the first III-V semiconductor material and the second III-V semiconductor material is indium gallium antimonide.

12. An integrated circuit device, comprising:

a first transistor including a first channel region over a first buffer, the first channel region formed of a first channel material, the first channel region interposed between first source/drain regions, the first source/drain regions formed of a first III-V semiconductor material, the first channel region formed from a first channel material; and

a second transistor including a second channel region over a second buffer, the second channel region formed of a second channel material, the second channel region interposed between second source/drain regions, the second source/drain regions formed of a second III-V semiconductor material, the first III-V semiconductor material and the second III-V semiconductor material comprising a same type of elements with different chemical formulas, the first transistor and the second transistor being field effect transistors of a same conductivity type;

wherein one of the first channel region and the second channel region is subjected to a compressive strain, and another of the first channel region and the second channel region is subjected to a tensile strain;

wherein a first strain introduced by a lattice mismatch between the first III-V semiconductor material and the first channel material is different than a second strain introduced by a lattice mismatch between the second III-V semiconductor material and the second channel material; and

wherein the first channel material and the second channel material comprise a same III-V semiconductor material having a same ratio of elements.

13. The integrated circuit device of claim 12 , wherein the first III-V semiconductor material has a lower concentration of indium than the second III-V semiconductor material.

14. The integrated circuit device of claim 12 , wherein the first III-V semiconductor material, the second III-V semiconductor material, the first channel material, and the second channel material comprises indium and gallium, the first III-V semiconductor material having a lower concentration of indium than the first channel material, the second III-V semiconductor material having a higher concentration of indium that the second channel material.

15. The integrated circuit device of claim 12 , wherein the first buffer and the second buffer is formed of indium aluminum arsenide.

16. An integrated circuit device comprising:

a first transistor including a first channel over a first buffer, first source/drain regions on opposing sides of the first channel, the first source/drain regions formed of a first III-V semiconductor material, the first channel formed of a second III-V semiconductor material, the first transistor having a first threshold voltage; and

a second transistor including a second channel over a second buffer, second source/drain regions on opposing sides of the second channel, the second source/drain regions formed of a third III-V semiconductor material, the second channel formed of a fourth III-V semiconductor material, the first transistor and the second transistor being field effect transistors of a same conductivity type, the second transistor having a second threshold voltage, the first threshold voltage being different from the second threshold voltage, the first channel and the second channel being subjected to opposite strains;

wherein the first III-V semiconductor material, the second III-V semiconductor material, and the third III-V semiconductor material having a same combination of elements with differing chemical formulas; and

wherein the second III-V semiconductor material and the fourth III-V semiconductor material have a same chemical formula.

17. The integrated circuit device of claim 16 , wherein the first III-V semiconductor material, the second III-V semiconductor material, the third III-V semiconductor material, and the fourth III-V semiconductor material is indium gallium arsenide.

18. The integrated circuit device of claim 16 , wherein the first III-V semiconductor material has a lower concentration of indium than the second III-V semiconductor material, and wherein the third III-V semiconductor material has a higher concentration of indium than the second III-V semiconductor material.

19. The integrated circuit device of claim 16 , wherein the first III-V semiconductor material and the second III-V semiconductor material is indium gallium antimonide.

20. The integrated circuit device of claim 1 , wherein the second transistor has a higher threshold voltage than the first transistor.