IP Library Granted Patent US 9,337,132
Granted Patent B2
US 9,337,132 · App. 14/052,711 · Granted May 10, 2016

Methods and configuration for manufacturing flip chip contact (FCC) power package

Inventors: Ming Sun (Sunnyvale, CA); Kai Liu (Sunnyvale, CA); Xiaotian Zhang (San Jose, CA); Yueh Se Ho (Sunnyvale, CA); Leeshawn Luo (Santa Clara, CA)
Assignee: Alpha and Omega Semiconductor Incorporated
H01L23/49562H01L23/492H01L23/4928H01L24/83H01L24/97H01L29/66477H01L29/78H01L24/29H01L24/32H01L24/33H01L2224/291H01L2224/32245H01L2224/33181H01L2224/8385H01L2224/83205H01L2224/83801H01L2224/83895H01L2224/97H01L2924/13091H01L2924/181
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Quick Facts
Patent No.
US 9,337,132
App. No.
14/052,711
Granted
May 10, 2016
Kind
B2
Abstract

A power device package for containing, protecting and providing electrical contacts for a power transistor includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy.

Claims (16)

1. A method for manufacturing a power device package comprising:

manufacturing a power transistor as an integrated circuit (IC) chip on a semiconductor die wherein the IC chip having a top flat-surface die electrode and at least a bottom flat-surface die electrode wherein the power device package further containing, protecting and providing electrical contacts for the IC chip;

forming the power device package with a leadframe comprises a top metal plate as an integral part of the leadframe for directly soldering to and contacting substantially a majority area of the top flat-surface die electrode of the IC chip without any intermediate bonding or attachment layer between the top metal plate and the top flat-surface die electrode; and

forming the power device package with the leadframe further comprises a bottom metal plate as an integral part of the leadframe for directly soldering to and contacting substantially a majority area of the bottom flat-surface die electrode of the IC chip without any intermediate bonding or attachment layer between the bottom metal plate and the bottom flat-surface die electrode.

2. The method of claim 1 wherein:

said step of manufacturing a power transistor as an IC chip further comprising a step of manufacturing the IC chip as a flip chip having the top flat-surface die electrode and the bottom flat-surface die electrode for directly soldering and contacting respectively the top and bottom metal plates as an integral part of the leadframe.

3. The method of claim 1 wherein:

said step of manufacturing a power transistor as an IC chip further comprising a step of manufacturing the IC chip as a MOSFET flip chip having the bottom flat-surface die electrode comprises a flat-surface source electrode and a flat-surface gate electrode and the top flat-surface die electrode comprises a flat-surface drain electrode for directly soldering and contacting respectively the bottom and top metal plates as an integral part of the leadframe.

4. The method of claim 1 wherein:

said steps of directly soldering the top and bottom metal plates to the top and bottom flat-surface die electrodes of the IC chip respectively further comprising a step of directly soldering a top aluminum plate and a bottom aluminum bottom plate as the integral parts of the leadframe to the top and bottom flat-surface die electrodes of the IC chip respectively.

5. The method of claim 1 wherein:

said steps of directly soldering the top and bottom metal plates to the top and bottom flat-surface die electrodes of the IC chip respectively further comprising a step of directly soldering a top copper plate and a bottom copper bottom plate as the integral parts of the leadframe to the top and bottom flat-surface die electrodes of the IC chip respectively.

6. The method of claim 1 wherein:

said steps of directly soldering the top and bottom metal plates to the top and bottom flat-surface die electrodes of the IC chip respectively further comprising a step of directly soldering a top sliver plate and a bottom sliver bottom plate as the integral parts of the leadframe to the top and bottom flat-surface die electrodes of the IC chip respectively.

7. The method of claim 1 wherein:

said steps of directly soldering the top and bottom metal plates to the top and bottom flat-surface die electrodes of the IC chip respectively further comprising a step of directly soldering a top nickel plate and a bottom nickel bottom plate as the integral parts of the leadframe to the top and bottom flat-surface die electrodes of the IC chip respectively.

Continuity (3)
Division 11894240 · Mar 31, 2008
Continuation 11027081 · Dec 31, 2004
Related Publication 20150102425A1 · Apr 16, 2015