FinFET with multiple dislocation planes and method for forming the same
A device comprises a first semiconductor fin over a substrate, a second semiconductor fin over the substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by a first isolation region, a first drain/source region coupled to the first semiconductor fin and the second semiconductor fin and a first dislocation plane underlying the first isolation region, wherein the first dislocation plane extends in a first direction in parallel with a longitudinal axis of the first semiconductor fin.
1. A device comprising:
a first semiconductor fin over a substrate;
a second semiconductor fin over the substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by a first isolation region;
a first drain/source region coupled to the first semiconductor fin and the second semiconductor fin; and
a first dislocation plane underlying the first isolation region, wherein the first dislocation plane extends in a first direction in parallel with a longitudinal axis of the first semiconductor fin.
2. The device of claim 1 , further comprising:
a second dislocation plane underlying the first drain/source region, wherein the second dislocation plane extends in a second direction.
3. The device of claim 2 , wherein:
the first direction is orthogonal to the second direction.
4. The device of claim 1 , further comprising:
a second drain/source region coupled to the first drain/source region through a channel region; and
a gate structure comprising a gate dielectric layer and a gate electrode layer.
5. The device of claim 4 , wherein:
the gate electrode layer wraps the channel region around three sides.
6. The device of claim 4 , wherein:
the first drain/source region, the second drain/source region and the gate structure form an n-type transistor.
7. The device of claim 1 , wherein:
the first isolation region is a shallow trench isolation region.
8. A device comprising:
a first semiconductor fin and a second semiconductor fin over a substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by a first isolation region;
a first drain/source region coupled to the first semiconductor fin and the second semiconductor fin;
a first dislocation plane underlying the first isolation region, wherein the first dislocation plane extends in a first direction; and
a second dislocation plane underlying the first drain/source region, wherein the second dislocation plane extends in a second direction orthogonal to the first direction.
9. The device of claim 8 , further comprising:
a second drain/source region coupled to the first semiconductor fin and the second semiconductor fin, wherein the first drain/source region is coupled to the second drain/source region through a channel region.
10. The device of claim 9 , wherein:
the first dislocation plane and the channel region are parallel to each other.
11. The device of claim 9 , further comprising:
a gate structure wrapping the channel region around three sides.
12. The device of claim 11 , wherein:
the first drain/source region, the second drain/source region and the gate structure form an n-type fin field-effect-transistor.
13. The device of claim 8 , further comprising:
a third semiconductor fin over the substrate, wherein the third semiconductor fin and the second semiconductor fin are separated by a second isolation region; and
a third dislocation plane underlying the second isolation region.
14. The device of claim 13 , wherein:
the first dislocation plane and the third dislocation plane are parallel to each other.
15. A device comprising:
a first fin, a second fin, a third fin and a fourth fin over a substrate, wherein:
the first fin and the second fin are separated by a first isolation region; and
the third fin and the fourth fin are separated by a second isolation region;
a first drain/source region and a second drain/source region on opposite sides of the first fin;
a first dislocation plane underlying the first isolation region;
a second dislocation plane underlying the second isolation region, wherein the first dislocation plane and the second dislocation plane are parallel to each other;
a third dislocation plane underlying the first drain/source region; and
a fourth dislocation plane underlying the second drain/source region, wherein:
the third dislocation plane and the fourth dislocation plane are parallel to each other; and
the second dislocation plane is orthogonal to the fourth dislocation plane.
16. The device of claim 15 , further comprising:
a channel region coupled between the first drain/source region and the second drain/source region.
17. The device of claim 15 , further comprising:
a third isolation region between the second fin and the third fin; and
a fifth dislocation plane underlying the third isolation region, wherein the first dislocation plane and the fifth dislocation plane are parallel to each other.
18. The device of claim 17 , further comprising:
a gate structure comprising a gate dielectric layer and a gate electrode layer, wherein the gate structure wraps the first fin around three sides.
19. The device of claim 18 , wherein:
the first drain/source region, the second drain/source region and the gate structure form an n-type transistor.
20. The device of claim 15 , wherein:
the first isolation region and the second isolation region are shallow trench isolation regions.