IP Library Granted Patent US 9,362,321
Granted Patent B2
US 9,362,321 · App. 13/289,086 · Granted Jun 7, 2016

Solid-state imaging device and manufacturing method thereof

Inventor: Kazuichiro Itonaga (Tokyo, JP)
Assignee: SONY CORPORATION
H01L27/14609H01L27/14689H01L27/14603H01L27/14643H01L31/035281
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Quick Facts
Patent No.
US 9,362,321
App. No.
13/289,086
Granted
Jun 7, 2016
Kind
B2
Abstract

A solid-state imaging device includes a photoelectric conversion unit, a transistor, and an element separation region separating the photoelectric conversion unit and the transistor. The photoelectric conversion unit and the transistor constitute a pixel. The element separation region is formed of a semiconductor region of a conductivity type opposite to that of a source region and a drain region of the transistor. A part of a gate electrode of the transistor protrudes toward the element separation region side beyond an active region of the transistor. An insulating film having a thickness substantially the same as that of a gate insulating film of the gate electrode of the transistor is formed on the element separation region continuing from a part thereof under the gate electrode of the transistor to a part thereof continuing from the part under the gate electrode of the transistor.

Claims (22)

1. A solid-state imaging device comprising:

a gate electrode of a first transfer transistor between a floating diffusion unit and a first photodiode in a layout of a pixel array;

a gate electrode of a second transfer transistor between the floating diffusion unit and a second photodiode in the layout of the pixel array;

a gate electrode of a selection transistor between a first semiconductor region and a second semiconductor region in the layout of the pixel array;

a gate electrode of an amplification transistor between the second semiconductor region and a third semiconductor region in the layout of the pixel array; and

an element separation region between the first photodiode and the gate electrode of the amplification transistor in the layout of the pixel array,

wherein the gate electrode of the amplification transistor extends over a part of the element separation region.

2. The solid-state imaging device according to claim 1 , wherein the first semiconductor region and the second semiconductor region are of a first conductivity-type, the element separation region is of a second conductivity-type.

3. The solid-state imaging device according to claim 2 , wherein the first conductivity-type is N-type and the second conductivity-type is P-type.

4. The solid-state imaging device according to claim 2 , wherein the floating diffusion unit is of the first conductivity-type.

5. The solid-state imaging device according to claim 2 , wherein the first conductivity-type is opposite to the second conductivity-type.

6. The solid-state imaging device according to claim 1 , wherein the first transfer transistor is controllable to provide an electrical connection and disconnection between the floating diffusion unit and the first photodiode.

7. The solid-state imaging device according to claim 1 , wherein the second transfer transistor is controllable to provide an electrical connection and disconnection between the floating diffusion unit and the second photodiode.

8. The solid-state imaging device according to claim 1 , wherein the gate electrode of the amplification transistor is electrically connected to the floating diffusion unit.

9. The solid-state imaging device according to claim 1 , further comprising:

a first line electrically connected to the gate electrode of the first transfer transistor.

10. The solid-state imaging device according to claim 9 , further comprising:

a second line electrically connected to the gate electrode of the second transfer transistor.

11. The solid-state imaging device according to claim 1 , further comprising:

a gate electrode of a reset transistor between the third semiconductor region and a fourth semiconductor region in the layout of the pixel array.

12. The solid-state imaging device according to claim 11 , wherein the first semiconductor region and the third semiconductor region are of a same conductivity-type, the second semiconductor region and the fourth semiconductor region are of the same conductivity-type.

13. The solid-state imaging device according to claim 11 , wherein the fourth semiconductor region is electrically connected to the floating diffusion unit.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE ZIP CODE FROM 246-0014 TO 243-0014 PREVIOUSLY RECORDED AT REEL: 039645 FRAME: 0019. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 13, 2016
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 040894/0926 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2016
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 039645/0019 →
Priority Claims (1)
JP 2007-148642 · Jun 4, 2007 · national
Continuity (2)
Continuation 12153023 · May 13, 2008
Related Publication 20120049254A1 · Mar 1, 2012