Method of deriving switch current signals in a rectifier
A method of deriving synchronous switch currents for a three-phase Vienna-type active rectifier that includes the step of generating gate driver signals for each phase of the rectifier by pulse width modulation, wherein the gate driver signals include a top gate driver signal, a clamp gate driver signal and a bottom gate driver signal, and the step of deriving synchronous switch current signals from the gate driver signal, wherein the synchronous switch current signals include a top gate switch current signal, a clamp gate switch current signal and a bottom gate switch current signal.
1. A method of deriving switch current signals in a rectifier comprising the step of:
sensing a line current signal from current applied to a phase leg of a VIENNA-type rectifier;
applying the line current signal to a first analog switch, a second analog switch, and a third analog switch;
generating a top gate driver signal, a clamp gate driver signal, and a bottom gate driver signal by pulse width modulation;
deriving a top switch current signal by driving the first analog switch using the top gate driver signal;
deriving a clamp switch current signal by driving the second analog switch using the clamp gate driver signal; and
deriving a bottom switch current signal by driving the third analog switch using the bottom gate driver signal.
2. A method according to claim 1 , further comprising the step of first analog switch driven by a top gate driver signal, a second analog switch driven by a clamp gate driver signal and a third analog switch driven by a bottom gate driver signal.
3. A method according to claim 1 , further comprising the step of the sensing line current signal upstream from the analog switches.
4. A method according to claim 1 , wherein the gate driver signals are generated by a pulse width modulator.
5. A method according to claim 1 , wherein the gate driver signals include a top gate driver signal, a clamp gate driver signal and a bottom gate driver signal.
6. A method according to claim 5 , wherein the top and bottom gate driver signals are delayed with respect to the clamp gate driver signal.
7. A method according to claim 1 , wherein the step of generating the gate driver signals includes the step of comparing a nearly sinusoidal control signal with two triangular waveforms.
8. A method of deriving synchronous switch current signals for a three-phase rectifier comprising the step of:
for each phase leg of a three-phase VIENNA-type rectifier:
sensing a line current signal from current applied to the phase leg;
applying the line current signal to a first analog switch, a second analog switch, and a third analog switch;
generating a top gate driver signal, a clamp gate driver signal, and a bottom gate driver signal by pulse width modulation;
deriving a top switch current signal by driving the first analog switch using the top gate driver signal;
deriving a clamp switch current signal by driving the second analog switch using the clamp gate driver signal; and
deriving a bottom switch current signal by driving the third analog switch using the bottom gate driver signal.
9. A method according to claim 8 , further comprising the step of current signal upstream from the analog switches.
10. A method according to claim 8 , further comprising the step of generated by a pulse width modulator.
11. A method according to claim 8 , wherein the gate driver signals include a top gate driver signal, a clamp gate driver signal and a bottom gate driver signal.
12. A method according to claim 11 , wherein the top and bottom gate driver signals are delayed with respect to the clamp gate driver signal.
13. A method according to claim 1 , wherein the step of generating the gate driver signals includes the step of comparing a nearly sinusoidal control signal with two triangular waveforms.
14. A method of deriving synchronous switch current signals for a three-phase Vienna-type active rectifier comprising the step of:
for each phase leg of a three-phase VIENNA-type rectifier:
sensing a line current signal from current applied to the phase leg;
applying the line current signal to a first analog switch, a second analog switch, and a third analog switch;
generating a top gate driver signal, a clamp gate driver signal, and a bottom gate driver signal by pulse width modulation;
deriving a top switch current signal by driving the first analog switch using the top gate driver signal;
deriving a clamp switch current signal by driving the second analog switch using the clamp gate driver signal; and
deriving a bottom switch current signal by driving the third analog switch using the bottom gate driver signal.
15. A method according to claim 14 , further comprising the step of sensed line current signals upstream from the analog switches.
16. A method according to claim 14 , further comprising the step of signals are delayed with respect to the clamp gate driver signal.