Semiconductor device and method of manufacturing the same

1. A method of manufacturing a semiconductor device, the method comprising:

forming an active pattern on a semiconductor substrate, the active pattern protruding and extending from the semiconductor substrate;

forming a dummy gate pattern crossing over the active pattern;

forming gate spacers on opposite first and second sidewalls of the dummy gate pattern;

forming source and drain electrodes disposed on the active pattern at both sides of the dummy gate pattern;

removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers;

recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region disposed between the source and drain electrodes;

forming a channel pattern in the channel recess region by a selective epitaxial growth (SEG) process, the channel pattern having sidewalls and having a lattice constant different from that of the semiconductor substrate; and

forming a gate dielectric layer and a gate electrode covering an upper surface and the sidewalls of the channel pattern in the gate region.

2. The method of claim 1 , further comprising:

forming a mold pattern covering the sidewalls of the active pattern in the gate region before the formation of the channel recess region, the mold pattern exposing the upper surface of the active pattern in the gate region,

wherein the mold pattern defines the sidewalls of the channel pattern.

3. The method of claim 2 , further comprising:

removing the mold pattern to expose the sidewalls of the channel pattern before the formation of the gate dielectric layer and the gate electrode.

4. The method of claim 1 , further comprising:

forming a device isolation layer exposing a sidewall of an upper portion of the active pattern before the formation of the dummy gate pattern,

wherein a recessed upper surface of the active pattern in the channel recess region is lower than an upper surface of the device isolation layer.

5. The method of claim 1 , wherein bottom surfaces of the gate spacers are in contact with an upper surface of the active pattern.

6. The method of claim 1 , wherein the upper surface of the channel pattern is lower than bottom surfaces of the gate spacers.

7. The method of claim 1 , wherein a width of an upper portion of the channel pattern is greater than a width of a lower portion of the channel pattern in contact with the active pattern.

8. The method of claim 1 , wherein an upper surface of the semiconductor substrate has a (100) crystal plane, and

wherein the sidewall of the channel pattern has a (110) crystal plane.

9. The method of claim 1 , wherein the forming the source and drain electrodes occurs before the removing the dummy gate pattern.

10. A method of manufacturing a semiconductor device, the method comprising:

forming an active pattern on a semiconductor substrate, the active pattern protruding and extending from the semiconductor substrate;

forming source and drain electrodes disposed on the active pattern and spaced apart from each other;

recessing an upper surface of the active pattern between the source and drain electrodes to form a channel recess region;

forming a channel pattern in the channel recess region by a selective epitaxial growth (SEG) process, the channel pattern having sidewalls and having a lattice constant different from that of the semiconductor substrate; and

forming a gate dielectric layer and a gate electrode crossing over the active pattern and covering an upper surface and the sidewalls of the channel pattern,

wherein the channel pattern is disposed between the source and drain electrodes.

11. The method of claim 10 , further comprising:

forming a dummy gate pattern crossing over the active pattern before the formation of the source and drain regions;

forming gate spacers on opposite first and second sidewalls of the dummy gate pattern; and

removing the dummy gate pattern to form a gate region exposing the upper surface and sidewalls of the active pattern between the gate spacers before recessing the upper surface of the active pattern.

12. The method of claim 11 , further comprising:

forming a mold pattern covering the sidewalls of the active pattern in the gate region before the formation of the channel recess region, the mold pattern exposing the upper surface of the active pattern in the gate region,

wherein the mold pattern defines the sidewall of the channel pattern.

13. The method of claim 12 , further comprising removing the mold pattern to expose the sidewall of the channel pattern before the formation of the gate dielectric layer and the gate electrode.

14. The method of claim 12 , wherein the gate spacers are disposed between the source and drain regions, and

wherein the channel pattern is disposed between the gate spacers.

15. The method of claim 11 , further comprising:

forming a device isolation layer exposing a sidewall of an upper portion of the active pattern before the formation of the dummy gate pattern,

wherein a recessed upper surface of the active pattern in the channel recess region is lower than an upper surface of the device isolation layer.

16. The method of claim 10 , wherein the upper surface of the channel pattern is rounded.

17. A method of manufacturing a semiconductor device, the method comprising:

patterning a semiconductor substrate to form active patterns extending from the semiconductor substrate;

forming a dummy gate pattern crossing over the active patterns;

forming gate spacers on both sidewalls of the dummy gate pattern;

forming source and drain electrodes disposed on the active pattern at both sides of the dummy gate pattern;

removing the dummy gate pattern to form a gate region exposing upper surfaces and sidewalls of the active patterns between the gate spacers;

forming a mold pattern filling a space between the active patterns in the gate region, the mold pattern exposing the upper surfaces of the active patterns in the gate region;

recessing the upper surfaces of the active patterns exposed by the mold pattern to form a channel recess region exposing a sidewall of the mold pattern in the gate region;

forming a channel pattern in the channel recess region by a selective epitaxial growth (SEG) process, the channel pattern disposed between the source and drain electrodes and having sidewalls and having a lattice constant different from that of the semiconductor substrate; and

forming a gate dielectric layer and a gate electrode covering an upper surface and the sidewalls of the channel pattern in the gate region.

18. The method of claim 17 , wherein the channel pattern is in contact with the sidewall of the mold pattern when the selective epitaxial growth (SEG) process is performed, and

the method further comprising:

removing the mold pattern to expose the sidewalls of the channel pattern before the formation of the gate dielectric layer and the gate electrode.

19. The method of claim 17 , further comprising forming a device isolation layer exposing sidewalls of upper portions of the active patterns before the formation of the dummy gate pattern,

wherein recessed upper surfaces of the active patterns in the channel recess region are lower than an upper surface of the device isolation layer.

20. The method of claim 17 , wherein the forming the source and drain electrodes occurs before the removing the dummy gate pattern.