Stacked switched capacitor energy buffer circuit architecture
Described herein is a stacked switched capacitor (SSC) energy buffer circuit architecture and related design and control techniques.
1. A grid interface power converter system comprising:
a stacked switched capacitor (SSC) energy buffer circuit coupled between a DC-DC converter and an AC-DC converter, said stacked switched capacitor (SSC) energy buffer circuit comprising:
two sub-circuits that serially coupled during a first operating mode wherein each sub-circuit comprises one or more capacitors, and at least one sub-circuit further comprises a plurality of switches disposed to selectively couple the capacitors to: (a) enable dynamic reconfiguration of how the capacitors are coupled to the terminals of the subcircuit; and (b) dynamically reconfigure the interconnection among the capacitors within the subcircuit.
2. The circuit of claim 1 said SSC energy buffer circuit comprises:
a first set of circuitry comprising:
m capacitors; and
m switches, each in switch serially coupled to a corresponding one of the m capacitors; and
a second set of circuitry comprising:
n capacitors; and
n switches, each n switch in series with a corresponding one of the n capacitors;
wherein a voltage across the first set of circuitry and the second set of circuitry is a bus voltage.
3. The circuit of claim 1 wherein the SSC energy buffer circuit is configured to maintain the bus voltage within ±12.5% of a nominal value.
4. The SSC energy buffer circuit of claim 1 wherein the switches in at least one of the two sub-circuits are arranged to dynamically reconfigure a polarity with which at least one capacitor is connected to the terminals of the sub-circuit.
5. The SSC energy buffer circuit of claim 1 , further comprising a pre-charge circuit coupled to each of the two sub-circuits said pre-charge circuit operable to charge each of the one or more capacitors in the two sub-circuits to specified initial conditions before entering the first operating mode.
6. The SSC energy buffer circuit of claim 1 wherein at least one subcircuit comprises a plurality of sub-sub-circuits connected in parallel, wherein each sub-sub-circuit comprises a switch serially coupled to a capacitor.
7. The SSC energy buffer circuit of claim 1 wherein the peak energy storage capability of one of the two sub-circuits is greater than 66% of the total peak energy storage capability.