System and method of detecting design rule noncompliant subgraphs in circuit netlists
View Patent ↗An automated system and method of performing electronic design rule checking on the netlist of an integrated circuit composed of a plurality of subgraphs. The electronic design rule is embodied as a two part template with a target subgraph specification and a design rule compliance check specification. The target subgraph specification often is at least partially defined by an interactive visual programming section that allows the user to construct a graphic specification of the target netlist. The method first searches the netlist for target subgraphs that match the target subgraph specification, and the user can verify proper target selection. The method then performs rule checks on these search targets, and non compliant subnets identified. Flexibility is enhanced by use of search wildcards, attribute ranges, and various short user scripts which may contain various Boolean logical operations.
1. A computer implemented method of checking electronic circuit netlists for compliance to at least one design rule, said method comprising:
providing a computer non-transitory readable netlist of an integrated circuit to be tested, said netlist comprising a plurality of subgraphs and candidate circuit elements;
defining a template for at least one design rule, said at least one design rule comprising a candidate identifier portion and a design rule compliance portion;
wherein said candidate identifier portion of said design rule comprises at least one wildcard or at least one ranged attribute;
wherein said design rule compliance portion of said design rule further comprises rules to determine components or connections that are missing from said first set of target subgraphs;
using said candidate identifier portion of said at least one design rule to define at least one subgraph and/or candidate circuit element to be tested, wherein said at least one subgraph or candidate circuit element to be tested are defined by either their net name pattern, connected device name pattern, arrangement of circuit components, or block of Boolean logic candidate selection rules;
wherein said net name pattern, connected device name pattern, arrangement of circuit elements, or block of Boolean logic candidate selection rules comprises at least one wildcard or at least one ranged attribute;
further using the graphical user interface of a computer to input a graphical pattern comprising a collection of one or more electronic devices and/or building blocks to at least partially define said candidate identifier portion of said at least one design rule;
wherein said building blocks comprise at least one building block selected from the group consisting of IO pad definition, IO directionality definition, Primary high clamps, Primary low clamps, series resistance in signal clamps, secondary high clamps, and secondary low clamps;
using a computer processor, said definition of at least one subgraph or candidate circuit element, said netlist, and said candidate identifier portion of said at least one design rule to perform a first search broadly identifying a first set of target candidate subgraphs; and
using a computer processor, said first set of target subgraphs and the design rule compliance portion of said at least one design rule to identify compliance of said first set of target subgraphs to the design rule compliance portion of said at least one design rule, thereby identifying design rule noncompliant subgraphs;
and either reporting or storing in memory said first set of target subgraphs and said design rule noncompliant subgraphs; and
wherein for at least some of said design rule noncompliant subgraphs, further reporting at least one of type of violation, number of similar violations, severity of violation, device name, circuit subgroup, or placement in the circuit.
2. The method of claim 1 , wherein said at least one Boolean logic candidate selection instruction comprises at least one instruction selected from the group consisting of an ESD clamp search instruction, a signal diode search instruction, a current reference search instruction, a current mirror search instruction, a voltage reference search instruction, a power switch search instruction, a digital stage search instruction, a band gap search instruction, an amplifier search instruction, a handcrafted digital search instruction, and a multiple voltage search instruction.
3. The method of claim 1 , further supplementing said graphical pattern with at least one Boolean logic candidate identifier instruction.
4. The method of claim 1 , wherein said graphical pattern defines at least one electronic device with at least one pin connection and at least one attribute, and wherein said at least one attribute further comprises a device geometry or a device name.