Central processing unit, GPU simulation method thereof, and computing system including the same

1. A single processor including a plurality of cores, comprising:

an upper core allocated with a main thread; and

a plurality of lower cores, each of the plurality of the lower cores being allocated with at least one worker thread,

wherein the single processor does not include a general purpose graphic processing unit (GPGPU),

the upper core and the plurality of lower cores do not include a graphic processing unit (GPU),

the single processor loads a GPU simulation code from a random access memory (RAM) or a nonvolatile memory device through a system bus,

the upper core transmits address information of the GPU simulation code associated with allocated simulation operations to the lower cores, based on the GPU simulation code,

each worker thread requests the GPU simulation code associated with the address information from the RAM, based on the received address information,

the plurality of the lower cores perform simulation operations on operation units of a virtual graphic processing unit (GPU), in the respective at least one worker thread, to generate simulation data, and

the upper core allocates the simulation operations on the operation units of the virtual GPU to the plurality of the worker threads and generates synchronization data based on the generated simulation data.

2. The single processor of claim 1 , wherein the main thread is an upper thread of the worker threads.

3. The single processor of claim 1 , wherein the upper core generates the plurality of the worker threads based on the number of the lower cores.

4. The single processor of claim 3 , wherein the upper core generates as many worker threads as the number of the lower cores.

5. The single processor of claim 1 , wherein the upper core generates the synchronization data based on the simulation data, when the simulation operations on the operation units of the virtual GPU are terminated.

6. A computing system, comprising:

a single processor; and

a random access memory (RAM) storing a graphic processing unit (GPU) simulation code,

wherein the single processor comprises:

an upper core associated with a main thread; and

a plurality of lower cores, each of the plurality of the lower cores being allocated with at least one worker thread,

wherein the single processor does not include a general purpose graphic processing unit (GPGPU), and the computing system does not include a GPU,

wherein the single processor loads the GPU simulation code from the RAM through a system bus,

the upper core transmits address information of the GPU simulation code associated with allocated simulation operations to the lower cores, based on the GPU simulation code,

each worker thread requests the GPU simulation code associated with the address information from the RAM, based on the received address information,

the plurality of the lower cores perform simulation operations on operation units of a virtual GPU, in the respective at least one worker thread, to generate simulation data, and

the upper core allocates the simulation operations on the operation units of the virtual GPU to a plurality of worker threads based on the GPU simulation code and generates synchronization data based on the generated simulation data.

7. The system of claim 6 , wherein the synchronization data constitutes data on the virtual GPU.

8. The system of claim 6 , wherein the upper core generates the plurality of worker threads based on the number of the lower cores.

9. The system of claim 6 , wherein the RAM stores the simulation data generated in the plurality of worker threads.

10. The system of claim 6 , wherein the RAM provides the simulation data generated in the simulation operations to the upper core, when the simulation operations on the operation units of the virtual GPU are terminated.

11. The system of claim 6 , wherein the generated synchronization data is stored in the RAM.

12. The system of claim 6 , wherein the upper core generates the synchronization data based on the simulation data, when the simulation operations on the operation units of the virtual GPU are terminated.

13. A method of performing a virtual graphic processing unit (GPU) simulation using a single processor with a plurality of cores, the method comprising:

generating a main thread and associating the main thread with one of the plurality of cores;

generating a plurality of worker threads and associating the plurality of the worker threads with remaining ones of the plurality of the cores, except the core associated with the main thread;

allocating simulation operations on operation units of the virtual GPU to the plurality of worker threads, according to a control from the core associated with the main thread;

performing the allocated simulation operations on the plurality of worker threads to generate simulation data; and

synchronizing the simulation data on the main thread,

wherein the plurality of cores do not include a graphic processing unit (GPU), and

wherein allocating simulation operations includes:

loading a GPU simulation code from a random access memory (RAM) or a nonvolatile memory device through a system bus, by the single processor, the single processor does not include a general purpose graphic processing unit (GPGPU),

transmitting address information of the GPU simulation code associated with the simulation operations to the remaining ones of the plurality of cores, based on the GPU simulation code, by the one of the plurality of cores, and

requesting the GPU simulation code associated with the address information from the RAM, based on the received address information, by each of the remaining ones of the plurality of the cores.

14. The method of claim 13 , wherein the generating of the plurality of the worker threads comprises generating the worker threads based on the number of the cores.

15. The method of claim 14 , wherein the synchronizing comprises synchronizing stored simulation data, when the allocated simulation operations are finished by the plurality of worker threads.