Amplifier with deterministic noise cancellation and method thereof
In one embodiment, a circuit comprising a passive input network of an input impedance configured to couple an input voltage to a first circuit node; an adaptive current source configured to output an adaptive bias current to the first circuit node; a cascode device controlled by a control voltage and configured to receive a sum current from the first circuit node and output an output current to a second circuit node; and a load network of a load impedance configured to provide termination to the second circuit node, wherein the adaptive bias current is dynamically adapted to track a deterministic noise component in the input voltage.
1. A circuit comprising:
a passive input network of an input impedance configured to couple an input voltage to a first circuit node;
an adaptive current source configured to output an adaptive bias current to the first circuit node;
a cascode device controlled by a control voltage and configured to receive a sum current from the first circuit node and output an output current to a second circuit node; and
a load network of a load impedance configured to provide termination to the second circuit node, wherein the adaptive bias current is dynamically adapted to track a deterministic noise component in the input voltage.
2. The circuit of claim 1 , wherein the passive input network comprises a series connection of a resistor and a capacitor.
3. The circuit of claim 1 , wherein the adaptive current source comprises a plurality of current sources configured to output a plurality of currents that can be conditionally passed to the first circuit node in accordance with a plurality of logical signals, respectively.
4. The circuit of claim 1 further comprises a gain boosting operational amplifier configured to receive a voltage at the first circuit node and output the control voltage.
5. The circuit of claim 1 , wherein the deterministic noise is an echo.
6. The circuit of claim 1 , wherein a gain factor is determined by a ratio between the load impedance and the input impedance.
7. The circuit of claim 1 , wherein the load impedance is tunable.
8. A circuit comprising:
a first passive input network of a first input impedance configured to couple a first input voltage to a first circuit node;
a second passive input network of a second input impedance configured to couple a second input voltage to the first circuit node;
an adaptive current source configured to output an adaptive bias current to the first circuit node;
a cascode device controlled by a control voltage and configured to receive a sum current from the first circuit node and output an output current to a second circuit node; and
a load network of a load impedance configured to provide termination to the second circuit node, wherein the adaptive bias current is dynamically adapted to track a deterministic noise component in one of the first input voltage and the second input voltage.
9. The circuit of claim 8 , wherein both the first passive input network and the second passive input network comprise a series connection of a resistor and a capacitor.
10. The circuit of claim 8 , wherein the adaptive current source comprises a plurality of current sources configured to output a plurality of currents that can be conditionally passed to the first circuit node in accordance with a plurality of logical signals, respectively.
11. The circuit of claim 8 further comprises a gain boosting operational amplifier configured to receive a voltage at the first circuit node and outputting the control voltage.
12. The circuit of claim 8 , wherein a first gain factor is determined by a ratio between the load impedance and the first input impedance and a second gain factor is determined by a ratio between the load impedance and the second input impedance.
13. The circuit of claim 8 , wherein the adaptive bias current is dynamically adapted to track a sum of a first deterministic noise component in the first input voltage and a second deterministic noise in the second input voltage.
14. A method comprising:
receiving an input voltage;
coupling the input voltage, using a passive input network, to a first circuit node;
providing an adaptive bias current to the first circuit node;
passing a sum current from the first circuit node to a second circuit node using a cascode device controlled by a control voltage;
terminating the second circuit node with a load network; and
adapting the adaptive bias current in accordance with a deterministic noise in the input voltage.
15. The method of claim 14 further comprising: dynamically adjusting the control voltage in accordance with a negative feedback from a voltage at the first circuit node.
16. The method of claim 15 , wherein the negative feedback comprises using an operational amplifier receiving the voltage at the first circuit node and outputting the control voltage.
17. A method comprising:
receiving a first input voltage;
coupling the first input voltage, using a first passive input network, to a first circuit node;
receiving a second input voltage;
coupling the second input voltage, using a second passive input network, to the first circuit node;
providing an adaptive bias current to the first circuit node;
passing a sum current from the first circuit node to a second circuit node using a cascode device controlled by a control voltage;
terminating the second circuit node with a load network; and
adapting the adaptive bias current in accordance with a deterministic noise in one of the input first input voltage and the second input voltage.
18. The method of claim 17 further comprising: dynamically adjusting the control voltage in accordance with a negative feedback from a voltage at the first circuit node.
19. The method of claim 18 , wherein the negative feedback comprises using an operational amplifier receiving the voltage at the first circuit node and outputting the control voltage.
20. The method of claim 17 , wherein the load network comprises a tunable resistor.