Smart semiconductor switch

1. A semiconductor device comprising:

a semiconductor substrate doped with dopants of a first type;

a vertical transistor composed of one or more transistor cells, each transistor cell having a first region formed in the substrate and doped with dopants of a second type; the first regions forming first pn-junctions with the surrounding substrate;

at least a first well region formed in the substrate and doped with dopants of a second type to form a second pn-junction with the substrate, the first well region being electrically connected to the first regions of the vertical transistor via a semiconductor switch;

and a detection circuit integrated in the substrate, wherein the detection circuit detects whether the first pn-junctions are reverse biased, wherein the switch is closed when the first pn-junctions are reverse biased and the switch is opened when the first pn-junctions are not reverse biased.

2. The semiconductor device of claim 1 ,

wherein the semiconductor switch includes a further transistor, which is a lateral transistor that is integrated in a second well region;

wherein the second well region is doped with dopants of a second type to form a third pn-junction with the substrate; and

wherein the second well region is electrically coupled to the first regions of the vertical transistor.

3. The semiconductor device of claim 2 ,

wherein the second well region is electrically connected to the first regions of the vertical transistor via a resistor.

4. The semiconductor device of claim 2 , wherein the further transistor is a lateral MOS transistor.

5. The semiconductor device of claim 4 ,

wherein the second well region is a body region of the further transistor.

6. The semiconductor device of claim 4 ,

wherein the detection circuit generates a gate signal to activate or deactivate the further transistor dependent on whether or not the first pn-junctions are not reverse biased.

7. The semiconductor device of claim 2 ,

wherein the detection circuit is integrated in a third well region which is doped with dopants of the second type to form a fourth pn-junction with the substrate.

8. The semiconductor device of claim 7 ,

wherein the third well region includes a collector region which is doped with dopants of the first type to form a fifth pn-junction with the third well region, the fourth and the fifth pn-junctions forming a bipolar junction transistor.

9. The semiconductor device of claim 7 ,

wherein the third well region includes a collector region which is doped with dopants of the first type to form a fifth pn-junction with the third well region, the fourth and the fifth pn-junctions forming a bipolar junction transistor; and

wherein the collector region is coupled to a gate electrode of the a further MOS transistor.

10. The semiconductor device of claim 9 ,

wherein the collector region is further connected to a supply potential via a resistor.

11. The semiconductor device of claim 1 ,

wherein the first well region includes at least one of: analog circuitry, digital logic circuitry, a gate driver circuit, communication circuitry, which are isolated from the substrate by a pn-junction isolation provided by the second pn-junction.

12. The semiconductor device of claim 1 , wherein the vertical transistor is a MOS transistor and the first regions are the body regions of the vertical transistor.

13. The semiconductor device of claim 1 , wherein the vertical transistor is composed a plurality of transistor cells having second regions; the second regions of the transistor cells being electrically connected to each other.

14. The semiconductor device of claim 13 , wherein the second regions of the transistor cells are coherently linked together.