IP Library Granted Patent US 9,411,540
Granted Patent B2
US 9,411,540 · App. 14/217,771 · Granted Aug 9, 2016

Efficient connection management in a SAS target

Inventor: Arie Peled (Tel-Mond, IL)
Assignee: Apple Inc.
G06F3/0661G06F3/068G06F3/0611G06F3/0617G06F3/0655G06F3/0689G11B5/09
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Quick Facts
Patent No.
US 9,411,540
App. No.
14/217,771
Granted
Aug 9, 2016
Kind
B2
Abstract

A method includes pre-configuring a hardware-implemented front-end of a storage device with multiple contexts of respective connections conducted between one or more hosts and the storage device. Storage commands, which are received in the storage device and are associated with the connections having the pre-configured contexts, are executed in a memory of the storage device using the hardware-implemented front-end. Upon identifying a storage command associated with a context that is not pre-configured in the hardware-implemented front-end, software of the storage device is triggered to configure the context in the hardware-implemented front-end, and the storage command is then executed using the hardware-implemented front-end in accordance with the context configured by the software.

Claims (33)

1. An apparatus, comprising:

a plurality of memory devices; and

a controller coupled to the plurality of memory devices, wherein the controller is configured to:

estimate data under-run at a host dependent upon a histogram of latency of data fetched from the plurality of memory devices;

determine a prefetch depth based on the estimated data under-run;

fetch data from at least one of the plurality of memory devices dependent upon the determined prefetch depth;

send the fetched data to the host; and

deactivate prefetching for a given memory device of the plurality of memory devices in response to a determination that the given memory device includes a Double Data Rate (DDR) memory.

2. The apparatus of claim 1 , wherein to estimate the data under-run, the controller is further configured to perform off-line characterization.

3. The apparatus of claim 1 , wherein to determine the prefetch depth, the controller is further configured to compare a probability of data under-run occurring to a predetermined value.

4. The apparatus of claim 1 , wherein to determine the prefetch depth, the controller is further configured to set the prefetch depth dependent upon a type of the given one of the plurality of memory devices.

5. A method, comprising:

estimating data under-run at a host dependent upon a histogram of latency of data fetched from a memory unit;

determine a prefetch depth based on estimated data under-run;

fetching data from the memory unit dependent upon the determined prefetch depth;

deactivating prefetching for a given memory device of the plurality of memory devices in response to a determination that the memory unit includes a Double Data Rate (DDR) memory; and

sending the fetched data to the host.

6. The method of claim 5 , wherein estimating the data under-run includes performing an off-line characterization.

7. The method of claim 5 , wherein determining the prefetch depth comprises comparing a probability of data under-run occurring to a predetermined value.

8. The method of claim 5 , wherein determining the prefetch depth comprises setting the prefetch depth dependent upon a type of the memory unit.

9. The method of claim 5 , wherein determining the prefetch depth comprises setting the prefetch depth dependent upon a total amount of data to be fetched from the memory unit.

10. A system, comprising:

a host; and

a memory unit, coupled to the host, wherein the memory unit includes a plurality of storage devices, and wherein the memory unit is configured to:

estimate data under-run at a host dependent upon a histogram of latency of data fetched from at least one of the plurality of storage devices;

determine a prefetch depth based on the estimated data under-run;

fetch data from at least one of the plurality of memory devices dependent upon the determined prefetch depth;

deactivate prefetching for a given memory device of the plurality of memory devices in response to a determination that the given memory device includes a Double Data Rate (DDR) memory; and

send the fetched data to the host.

11. The apparatus of claim 10 , wherein to estimate the data under-run, the memory unit is further configured to perform off-line characterization.

12. The apparatus of claim 10 , wherein to determine the prefetch depth, the memory unit is further configured to compare a probability of data under-run occurring to a predetermined value.

13. The apparatus of claim 10 , wherein to determine the prefetch depth, the memory unit is further configured to set the prefetch depth dependent upon a type of the given one of the plurality of storage devices.

14. The apparatus of claim 10 , wherein to determine the prefetch depth, the memory unit is further configured to set the prefetch depth dependent upon a total amount of data to be fetched from the plurality of storage devices.

Continuity (4)
Continuation 13439860 · Apr 5, 2012
Provisional Application 61476287 · Apr 17, 2011
Provisional Application 61528771 · Aug 30, 2011
Related Publication 20140201440A1 · Jul 17, 2014