Systems and methods for managing execution of specialized processors

1. A method of configuring one or more field programmable gate array (FPGA) modules for executing a primitive, the method comprising the steps of:

receiving at an FPGA-based controller an identifier of a primitive; and

using the FPGA-based controller to:

identify a plurality of FPGA units available for implementing the primitive;

select a plurality of subprimitives related to the primitive based, at least in part, on at least one of: (i) a primitive parameter and (ii) a system parameter, the plurality of subprimitives comprising a first subprimitive and a second subprimitive;

configure a first FPGA unit of the plurality of available FPGA units for executing the first subprimitive;

configure a second FPGA unit of the plurality of available FPGA units for executing the second subprimitive; and

configure at least a portion of an interconnect to coordinate the execution of the first subprimitive and the execution of the second subprimitive, the coordination comprising at least one of: (i) passing a result from the first FPGA unit to the second FPGA unit, and (ii) transmitting results from at least one of the first and second FPGA units to a memory unit.

2. The method of claim 1 , wherein:

the execution of the first subprimitive comprises accessing a first data element; and

the execution of the second subprimitive comprises accessing a second data element different from the first data element.

3. The method of claim 2 , wherein the second subprimitive comprises the first subprimitive.

4. The method of claim 2 , wherein:

the first data element is local to the first FPGA unit; and

the second data element is local to the second FPGA unit.

5. The method of claim 1 , wherein the first and the second FPGA units are configured to execute, at least partially in parallel, the first subprimitive and the second subprimitive.

6. The method of claim 1 , wherein the first FPGA unit and the second FPGA unit are configured to sequentially execute the first subprimitive and the second subprimitive.

7. The method of claim 1 , wherein:

the first FPGA unit is configured for using a first data element to generate an intermediate result; and

the second FPGA unit is configured for executing the second subprimitive using at least one of a second data element and the intermediate result.

8. The method of claim 7 , further comprising the step of:

providing an FPGA-based storage node manager configured to store the intermediate result in a storage module and to read the intermediate result from the storage module,

wherein the first and second FPGA units are configured to access the intermediate result via the FPGA-based storage node manager.

9. The method of claim 1 , further comprising configuring by the FPGA-based controller:

a third FPGA unit included in the plurality of available FPGA units to execute, using a third data element, a third subprimitive related to the primitive, wherein the plurality of subprimitives further includes the third subprimitive.

10. The method of claim 9 , wherein the configuration of the third FPGA unit by the FPGA-based controller is based on, at least in part, a size of data associated with the primitive.

11. The method of claim 9 , wherein the first FPGA unit is configured for generating an intermediate result, the method further comprising configuring by the FPGA-based controller:

activation of either the second FPGA unit or the third FPGA unit, based on, at least in part, the intermediate result.

12. The method of claim 1 , wherein the one or more FPGA modules comprise:

a first FPGA module comprising the first FPGA unit; and

a second FPGA module comprising the second FPGA unit.

13. The method of claim 1 , wherein:

the one or more FPGA modules comprise a first FPGA module comprising both a first FPGA processor and a second FPGA processor, and wherein:

the first FPGA processor comprises the first FPGA unit; and

the second FPGA processor comprises the second FPGA unit.

14. The method of claim 1 , wherein the one or more FPGA modules comprise a first FPGA processor comprising both the first FPGA unit and the second FPGA unit.

15. The method of claim 1 , further comprising, using the FPGA-based controller to:

configure all of the plurality of available FPGA units to execute a respective subprimitive selected from a first subset of the plurality of subprimitives such that the first FPGA unit is configured to execute the first subprimitive and the second FPGA unit is configured to execute the second subprimitive;

configure at least another portion of the interconnect to coordinate the execution of all of the first subset of the plurality of subprimitives in at least one of parallel, sequential, and conditional manner;

reconfigure all of the plurality of available FPGA units to execute a respective subprimitive selected from a second subset of the plurality of subprimitives related to the primitive; and

reconfigure at least the other portion of the interconnect to coordinate the execution of all of the second subset of the plurality of subprimitives in at least one of parallel, sequential, and conditional manner.

16. The method of claim 1 , wherein an intermediate subprimitive is related to the primitive, the method further comprising:

deriving by the FPGA-based controller the first and second subprimitives from the intermediate subprimitive, based on at least one of a primitive parameter and a system parameter.

17. A system for executing a primitive, the system comprising:

first and second FPGA units;

an interconnect; and

an FPGA-based controller configured to:

receive an identifier of a primitive,

identify a plurality of FPGA units available for implementing the primitive, the plurality of available FPGA units comprising the first and second FPGA units,

select a plurality of subprimitives related to the primitive based, at least in part, on at least one of: (i) a primitive parameter and (ii) a system parameter, the plurality of subprimitives comprising a first subprimitive and a second subprimitive,

configure the first FPGA unit to execute the first subprimitive,

configure the second FPGA unit to execute the second subprimitive, and

configure at least a portion of the interconnect to coordinate the execution of the first subprimitive and the second subprimitive, the coordination comprising at least one of: (i) passing a result from the first FPGA unit to the second FPGA unit, and (ii) transmitting results from at least one of the first and second FPGA units to a memory unit.

18. The system of claim 17 , wherein:

execution of the first subprimitive comprises the first FPGA unit accessing a first data element; and

execution of the second subprimitive comprises the second FPGA unit accessing a second data element different from the first data element.

19. The system of claim 18 , wherein the second subprimitive comprises the first subprimitive.

20. The system of claim 18 , wherein:

the first data element is local to the first FPGA unit; and

the second data element is local to the second FPGA unit.

21. The system of claim 17 , wherein the first and the second FPGA units are configured to execute, at least partially in parallel, the first subprimitive and the second subprimitive.

22. The system of claim 17 , wherein the first FPGA unit and the second FPGA unit are configured to sequentially execute the first subprimitive and the second subprimitive.

23. The system of claim 17 , wherein:

the first FPGA unit is configured to use a first data element to generate an intermediate result; and

the second FPGA unit is configured to execute the second subprimitive using at least one of a second data element and the intermediate result.

24. The system of claim 23 , further comprising an FPGA-based storage node manager configured to store the intermediate result in a storage module and to read the intermediate result from the storage module, wherein the first and second FPGA units are configured to access the intermediate result via the FPGA-based storage node manager.

25. The system of claim 17 , further comprising a third FPGA unit included in the plurality of available FPGA units, wherein the FPGA-based controller is further configured to configure the third FPGA unit to execute, using a third data element, a third subprimitive related to the primitive.

26. The system of claim 25 , wherein the configuration of the third FPGA unit by the FPGA-based controller is based on, at least in part, a size of data associated with the primitive.

27. The system of claim 25 , wherein the first FPGA unit is configured to generate an intermediate result, and wherein the FPGA-based controller is further configured to control activation of either the second FPGA unit or the third FPGA unit, based on, at least in part, the intermediate result.

28. The system of claim 17 , wherein the FPGA-based controller is further configured to:

configure all of the plurality of FPGA units to execute a respective subprimitive selected from a first subset of the plurality of subprimitives such that the first FPGA unit is configured to execute the first subprimitive and the second FPGA unit is configured to execute the second subprimitive;

configure at least another portion of the interconnect to coordinate the execution of all of the first subset of the plurality of subprimitives in at least one of parallel, sequential, and conditional manner;

reconfigure all of the plurality of FPGA units to execute a respective subprimitive selected from a second subset of the plurality of subprimitives; and

reconfigure at least the other portion of the interconnect to coordinate the execution of all of the second subset of the plurality of subprimitives in at least one of parallel, sequential, and conditional manner.

29. The system of claim 17 , wherein:

an intermediate subprimitive is related to the primitive; and

the FPGA-based controller is further configured to derive the first and second subprimitives from the intermediate subprimitive, based on at least one of a primitive parameter and a system parameter.

30. The system of claim 17 , wherein configuring at least the portion of the interconnect to coordinate the execution of the first subprimitive and the second primitive comprises selectively configuring at least the portion of the interconnect for at least one type of data flow selected from the group consisting of parallel data flow between a storage node manager and the first and second FPGA units, sequential data flow between the first and second FPGA units, and conditional data flow between the first and second FPGA units, and wherein the selectively configuring is based, at least in part, on a relationship between the first and second subprimitives.