Alternating tap-cell strategy in a standard cell logic block for area reduction

1. An integrated circuit comprising:

a plurality of N wells on a P substrate;

a plurality of tap columns located across the plurality of N wells on the P substrate;

a plurality of standard cells between the plurality of tap columns;

a plurality of tap cells disposed consecutively in the plurality of tap columns; each tap cell comprising a first tap active and a second tap active, wherein the first tap active of a first tap cell extends to the first tap active of a second tap cell which further extends to a well boundary of either the first tap cell or the second tap cell, and wherein, the first tap active of the first tap cell and the first tap active of the second tap cell are adjacent to each other in the tap column; and

two end tap cells, one located at a top end of the tap column and the other at a bottom end of the tap column, wherein the end tap cells are wider than the tap cells to accommodate logic blocks disposed adjacent to the plurality of tap columns and to meet the minimum area design rule associated with the integrated circuit.

2. The integrated circuit of claim 1 , wherein in adjacent tap cells, the first tap active of the first tap cell extends to the first tap active of the second tap cell which further extends to a well boundary to meet a minimum area design rule associated with the integrated circuit.

3. The integrated circuit of claim 1 , wherein the first tap active is located on the P substrate and the second tap active is located on the N-well.

4. The integrated circuit of claim 1 , wherein the first tap active is located on the N-well and the second tap active is located on the P substrate.

5. The integrated circuit of claim 1 , wherein the end tap cell further comprises:

a plurality of sub-tap cells in the end tap cell;

a second tap active of an adjacent tap cell extending to the second tap active of a first sub-tap cell and further extending to the well boundary of the adjacent tap cell;

the first tap active of the first sub-tap cell extending to the first tap active of a second sub-tap cell and further extending along the width of the end tap cell; and

an end tap active located within the end tap cell boundary and extending along the width of the end tap cell, wherein the end tap active is a last tap active in the tap column.

6. A method of manufacturing an integrated circuit, comprising:

disposing a plurality of N wells on a P substrate;

forming a plurality of tap columns across the plurality of N wells on the P substrate;

disposing a plurality of standard cells between the plurality of tap columns;

disposing a plurality of tap cells consecutively in the plurality of tap columns;

forming a first tap active and a second tap active in each tap cell of the plurality of tap cells; and

extending the first tap active of a first tap cell to the first tap active of a second tap cell which further extends to a well boundary of either the first tap cell or the second tap cell and, wherein the first tap active of the first tap cell and the first tap active of the second tap cell are adjacent to each other in the tap column; wherein forming a plurality of tap columns comprises:

disposing a plurality of the first tap cell and the second tap cell consecutively in each of the tap column;

disposing the first tap active of the first tap cell and the first tap active of the second tap cell consecutively across the tap column; and

forming an end tap cell at a top end and a bottom end of each of the tap column, wherein the end tap cell is wider than the tap cell to accommodate logic blocks placed adjacent to the plurality of tap columns and to meet the minimum area design rule associated with the integrated circuit.

7. The method of claim 6 , wherein extending the first tap active of a first tap cell to the first tap active of a second tap cell which further extends to a well boundary of either the first tap cell or the second tap cell in adjacent tap cells to meet a minimum area design rule associated with the integrated circuit.

8. The method of claim 6 further comprising forming the first tap active on the P substrate and forming the second tap active on the N-well.

9. The method of claim 6 further comprising forming the first tap active on the N-well and forming the second tap active on the P substrate.

10. The method of claim 6 , wherein each end tap cell further comprises plurality of tap actives and an end tap active.

11. The method of claim 6 , wherein forming the end tap cell comprises:

forming a plurality of sub-tap cells in the end tap cell;

extending the second tap active of an adjacent tap cell to the second tap active of a first sub-tap cell and further extending it to the well boundary of the adjacent tap cell;

extending the first tap active of the first sub-tap cell to the first tap active of a second sub-tap cell and further extending along the width of the end tap cell;

forming the end tap active within the end tap cell boundary, wherein the end tap active is a last tap active in the tap column; and

extending the end tap active along the width of the end tap cell.

12. An integrated circuit comprising:

a plurality of N wells on a P substrate;

a plurality of tap columns located across the plurality of N wells on the P substrate;

a plurality of standard cells between the plurality of tap columns;

a plurality of tap cells disposed consecutively in the plurality of tap columns; each tap cell comprising a first tap active and a second tap active, wherein the first tap active of a first tap cell extends to the first tap active of a second tap cell which further extends to a well boundary of either the first tap cell or the second tap cell, and wherein, the first tap active of the first tap cell and the first tap active of the second tap cell are adjacent to each other in the tap column; and

at least two end tap cells, one located at a top end of the tap column and the other at a bottom end of the tap column, wherein the end tap cells are wider than the tap cells.