IP Library Granted Patent US 9,419,637
Granted Patent B1
US 9,419,637 · App. 14/818,502 · Granted Aug 16, 2016

Multi-mode sampling/quantization converters

Inventor: Christopher Pagnanelli (Huntington Beach, CA)
Assignee: Syntropy Systems, LLC
H03M1/0626H03M1/36H03M3/322H03M3/38H03M3/414H03M3/468
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Quick Facts
Patent No.
US 9,419,637
App. No.
14/818,502
Granted
Aug 16, 2016
Kind
B1
Abstract

Provided are, among other things, systems, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. According to one implementation, an apparatus includes multiple processing branches, each including: a continuous-time quantization-noise-shaping circuit, a sampling/quantization circuit, and a digital bandpass filter. A combining circuit then combines signals at the processing branch outputs into a final output signal. The continuous-time quantization-noise-shaping circuits include adjustable circuit components for changing their quantization-noise frequency-response minimum, and the digital bandpass filters include adjustable parameters for changing their frequency passbands.

Claims (27)

1. An apparatus for converting a continuous-time, continuously variable signal into a sampled and quantized signal, comprising:

an input line for accepting an input signal that is continuous in time and continuously variable;

a plurality of processing branches having inputs coupled to the input line; and

a combining circuit, coupled to outputs of a plurality of said processing branches, that combines signals on said outputs into a final output signal,

wherein each of said processing branches includes: (a) a quadrature frequency downconverter, which uses discrete-time cosine and sine sequences to generate in-phase and quadrature outputs at baseband, (b) a first lowpass filter coupled to the in-phase output of the quadrature frequency downconverter, (c) a second lowpass filter coupled to the quadrature output of the quadrature frequency downconverter, and (d) a quadrature frequency upconverter coupled to outputs of the first and second lowpass filters, which uses discrete-time cosine and sine sequences to convert in-phase and quadrature inputs to a higher frequency output,

wherein the frequency response of each of said first and second lowpass filters has a magnitude that varies approximately with frequency according to the product of raised sin(x)/x functions, and

wherein each of a plurality of said processing branches includes at least one adjustable parameter which, when adjusted, changes at least one of: (i) a frequency of at least one of the cosine or sine sequences, or (ii) a bandwidth of at least one of the first lowpass filter or the second lowpass filter.

2. An apparatus according to claim 1 , wherein at least one of said first or said raised sin(x)/x functions included in said product for at least one of said first or said second lowpass filters is raised to a power that is equal to one.

3. An apparatus according to claim 1 , wherein at least one of said raised sin(x)/x functions included in said product for at least one of said first or said second lowpass filters is raised to a power that is greater than one.

4. An apparatus according to claim 1 , wherein the frequency response of at least one of said first or said second lowpass filters has a magnitude that varies approximately with frequency according to the product of a raised sin (x 1 )/x 1 function and a raised sin (x 2 )/x 2 function, where x 1 ≠x 2 .

5. An apparatus according to claim 4 , wherein x 1 ≧2x 2 .

6. An apparatus according to claim 1 , wherein the at least one adjustable parameter for at least one of said plurality of processing branches includes a first adjustable parameter which, when adjusted, changes a location of a frequency response passband of said at least one processing branch and a second adjustable parameter which, when adjusted, changes a bandwidth of said frequency response passband.

7. An apparatus according to claim 1 , wherein frequency responses of different ones of said processing branches are configured so as to select different frequency bands that collectively encompass an entire frequency range of the input signal.

8. An apparatus according to claim 1 , wherein different ones of the plurality of processing branches have substantially identical circuit configurations.

9. An apparatus according to claim 1 , wherein frequency responses of different ones of said processing branches are configured so as to have at least one of: (i) center frequencies that are spaced at non-equal intervals, and (ii) bandwidths that are not all equal to each other.

10. An apparatus according to claim 1 , wherein frequency responses of different ones of said processing branches are configured so as to have at least one of: (i) center frequencies that are spaced at equal intervals, and (ii) bandwidths that are all equal to each other.

11. An apparatus according to claim 1 , wherein at least one of the first and second lowpass filter responses is generated using a recursive operation.

12. An apparatus according to claim 1 , wherein at least one of the first and second lowpass filters is comprised of at least one moving-average component.

13. An apparatus according to claim 1 , wherein at least one of the lowpass filters includes a downsampling operation.

14. An apparatus according to claim 1 , wherein at least one of the cosine or sine sequences is generated using a lookup memory operation.

15. An apparatus according to claim 1 , wherein at least one of the cosine or sine sequences is generated using a recursive operation.

16. An apparatus according to claim 1 , wherein at least one of the first and second lowpass filters is implemented as a polyphase decomposition structure.

17. An apparatus according to claim 16 , wherein a polyphase decomposition factor, m, of the polyphase decomposition structure is a submultiple of the total number, M, of said processing branches.

18. An apparatus according to claim 1 , wherein the combining circuit permits real-time configuration for determining whether individual outputs of said plurality of said processing branches are to be merged into a single composite signal or are to retain their separate identities.

19. An apparatus according to claim 18 , wherein the combining circuit comprises an array of at least one adder for merging outputs of a plurality of said processing branches into a single composite signal and at least one multiplexer for multiplexing outputs to retain their separate identities.

20. An apparatus according to claim 18 , wherein there are exactly M said processing branches, M being a power of two.

21. An apparatus according to claim 1 , further comprising a sampling/quantization circuit having an input coupled to the input line and an output coupled to the inputs of the plurality of processing branches.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2021
From: PAGNANELLI, CHRISTOPHER; SYNTROPY SYSTEMS, LLC
To: PAGNANELLI FAMILY TRUST
Reel/Frame 057998/0246 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2021
From: SYNTROPY SYSTEMS, LLC
To: PAGNANELLI, CHRISTOPHER
Reel/Frame 055928/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2015
From: PAGNANELLI, CHRISTOPHER
To: SYNTROPY SYSTEMS, LLC
Reel/Frame 036255/0461 →
Continuity (6)
Continuation In Part 14558640 · Dec 2, 2014
Continuation In Part 13844948 · Mar 16, 2013
Continuation 12985214 · Jan 5, 2011
Provisional Application 61292428 · Jan 5, 2010
Provisional Application 61414413 · Nov 16, 2010
Provisional Application 61381055 · Sep 8, 2010