IP Library › Granted Patent US 9,424,034

Granted Patent B2

US 9,424,034 · App. 13/931,008 · Granted Aug 23, 2016

Multiple register memory access instructions, processors, methods, and systems

Inventors: Glenn Hinton (Portland, OR); Bret Toll (Hillsboro, OR); Ronak Singhal (Portland, OR)

Assignee: Intel Corporation

G06F9/30043 G06F9/30109

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Quick Facts

Patent No.: US 9,424,034
App. No.: 13/931,008
Granted: Aug 23, 2016
Kind: B2

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Abstract

A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

Claims (42)

1. A processor comprising:

a plurality of N-bit registers;

a decode unit to receive a multiple register memory access instruction, the multiple register memory access instruction to indicate a memory location and to indicate a register; and

a memory access unit coupled with the decode unit and with the plurality of the N-bit registers, the memory access unit to perform a multiple register memory access operation in response to the multiple register memory access instruction, the multiple register memory access operation to involve a different set of N-bit data, in each of the plurality of the N-bit registers that are to comprise the indicated register, which is to be one of loaded from and stored to, different corresponding N-bit portions of an M×N-bit line of memory, that is to correspond to the indicated memory location, in which a total number of bits of the different sets of N-bit data in the plurality of the N-bit registers to be involved in the multiple register memory access operation in total is to amount to at least half of the M×N-bits of the line of memory.

2. The processor of claim 1 , in which the memory access unit is to perform the operation in which the total number of bits of the different sets of N-bit data in the plurality of the N-bit registers to be involved in the multiple register memory access operation is to amount to all of the M×N-bits of the line of memory.

3. The processor of claim 1 , in which the memory access unit is to perform the operation in which the total number of bits of the different sets of N-bit data in the plurality of the N-bit registers to be involved in the multiple register memory access operation is to amount to at least 256-bits.

4. The processor of claim 3 , in which the memory access unit is to perform the operation in which the total number of bits of the different sets of N-bit data in the plurality of the N-bit registers to be involved in the multiple register memory access operation is to amount to at least 512-bits.

5. The processor of claim 1 , in which the memory access unit is to perform the operation that is to involve the N-bit data in each of at least three N-bit registers.

6. The processor of claim 5 , in which the memory access unit is to perform the operation that is to involve the N-bit data in each of at least four N-bit registers.

7. The processor of claim 1 , in which the memory access unit is to perform the operation that is to involve a different set of 128-bit data, in each of at least four 128-bit registers, and the different corresponding 128-bit portions of the line of memory that is to be at least 512-bits.

8. The processor of claim 1 , in which the memory access unit is to perform the operation that is to involve a different set of 256-bit data, in each of at least two 256-bit registers, and the different corresponding 256-bit portions of the line of memory that is to be at least 512-bits.

9. The processor of claim 1 , in which the processor comprises a reduced instruction set computing (RISC) processor, and in which the multiple register memory access instruction comprises a multiple register load from memory instruction, and in which the memory access unit is to load the different N-bit portions of the M×N-bit line of memory in the plurality of the N-bit registers, in response to the multiple register load from memory instruction, in which the total number of bits of the different N-bit portions to be loaded in the plurality of the N-bit registers from the M×N-bit line of memory is to amount to at least half of the M×N-bits of the line of memory.

10. The processor of claim 9 , in which the memory access unit is to load different 128-bit portions of the line of memory which is at least 512-bits in each of at least four 128-bit registers.

11. The processor of claim 9 , in which the memory access unit is to load different 256-bit portions of the line of memory which is at least 512-bits in each of at least two 256-bit registers.

12. The processor of claim 1 , in which the processor comprises a reduced instruction set computing (RISC) processor, and in which the multiple register memory access instruction comprises a multiple register write to memory instruction, and in which the memory access unit is to write the different sets of N-bit data, from the plurality of the N-bit registers, to the different corresponding N-bit portions of the M×N-bit line of memory, in response to the multiple register write to memory instruction, in which the total number of bits of the different sets of N-bit data to be written from the plurality of the N-bit registers to the M×N-bit line of memory is to amount to at least half of the M×N-bits of the line of memory, in which the at least half of the M×N-bits of the line of memory is at least 256-bits.

13. The processor of claim 1 , in which the multiple register memory access instruction is to explicitly specify each of the plurality of registers.

14. The processor of claim 1 , in which the multiple register memory access instruction is to specify a number of the plurality of registers.

15. A method performed by a processor comprising:

receiving a multiple register load from memory instruction, the multiple register load from memory instruction indicating a memory location and indicating a register; and

loading different N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location into each of a plurality of N-bit registers that comprise the indicated register, in response to the multiple register memory access instruction, in which a total number of bits of the different N-bit portions loaded into the plurality of the N-bit registers amounts to at least half of the M×N-bits of the line of memory.

16. The method of claim 15 , in which the total number of bits amounts to all of the M×N-bits of the line of memory.

17. The method of claim 15 , in which the total number of bits amounts to at least 256-bits.

18. The method of claim 17 , in which loading comprises loading the different N-bit portions into each of at least four N-bit registers.

19. The method of claim 15 , in which loading comprises loading different 128-bit portions into each of at least four 128-bit registers.

20. The method of claim 15 , in which loading comprises loading different 256-bit portions into each of at least two 256-bit registers.

21. A system to process instructions comprising:

an interconnect;

a dynamic random access memory (DRAM) coupled with the interconnect; and

a processor coupled with the interconnect, the processor, in response to a multiple register memory access instruction that is to indicate a memory location in the DRAM and a register, to perform a multiple register memory access operation that is to involve a different set of N-bit data, in each of a plurality of N-bit registers of the processor that are to comprise the indicated register, which is to be one of loaded from and stored to, different corresponding N-bit portions of an M×N-bit line of the DRAM that is to correspond to the indicated memory location, in which a total number of bits of the different sets of N-bit data in the plurality of the N-bit registers to be involved in the multiple register memory access operation in total is to amount to at least half of the M×N-bits of the line of memory.

22. The system of claim 21 , in which the total number of bits of the different sets of N-bit data in the plurality of the N-bit registers to be involved in the multiple register memory access operation is to amount to all of the M×N-bits of the line of memory which is at least 512-bits.

23. An article of manufacture comprising a non-transitory machine-readable storage medium storing a multiple register memory access instruction,

the multiple register memory access instruction to indicate a memory location and a register, and the multiple register memory access instruction if processed by a machine operable to cause the machine to perform operations comprising:

perform a multiple register memory access operation that is to involve a different set of N-bit data, in each of a plurality of N-bit registers that are to comprise the indicated register, which is to be one of loaded from and stored to, different corresponding N-bit portions of an M×N-bit line of memory, that is to correspond to the indicated memory location, in which a total number of bits of the different sets of N-bit data in the plurality of the N-bit registers to be involved in the multiple register memory access operation in total is to amount to at least half of the M×N-bits of the line of memory.

24. The article of manufacture of claim 23 , in which the total number of bits of the different sets of N-bit data in the plurality of the N-bit registers to be involved in the multiple register memory access operation is to amount to all of the M×N-bits of the line of memory which is at least 512-bits.

25. The processor of claim 1 , in which the memory access unit is to perform a multiple register load operation in response to the instruction, the multiple register load operation to load the N-bit data, in each of the plurality of the N-bit registers that are to comprise the indicated register from the different corresponding N-bit portions of the M×N-bit line of memory.

26. The processor of claim 1 , in which all data, in each of the plurality of the N-bit registers, is to be one of loaded from and stored to, the different corresponding N-bit portions of the M×N-bit line of memory.

27. The processor of claim 1 , in which at least two sequential registers of the plurality of N-bit registers are to be implicitly associated with the indicated register.

28. A processor comprising:

a plurality of N-bit registers;

a decode unit to receive a multiple register load from memory instruction, the multiple register load from memory instruction to indicate a memory location and to indicate a register; and

a memory access unit coupled with the decode unit and with the plurality of the N-bit registers, the memory access unit, in response to the multiple register load from memory instruction, to load different N-bit portions of an M×N-bit line of memory that is to correspond to the indicated memory location into corresponding ones of a plurality of corresponding N-bit registers that include the indicated register, in which a total number of bits of the different N-bit portions that are to be loaded into the N-bit registers is to amount to at least half of the M×N-bit line of memory.

29. The processor of claim 28 , in which the M×N-bit line of memory is to include at least 512-bits, in which each of the N-bit registers is to include at least 128-bits, and in which the N-bit registers are implicitly to be sequential registers.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2014

From: HINTON, GLENN; TOLL, BRET; SINGHAL, RONAK

To: INTEL CORPORATION

Reel/Frame 033613/0750 →

Continuity (1)

Related Publication 20150006848A1 · Jan 1, 2015