Nonvolatile memory system, method of operating the same and method of manufacturing the same
An operating method of a nonvolatile memory system including first and second areas is provided. Data stored in the first area is migrated to the second area when a first booting operation is performed. The data stored in the second area is reprogrammed. The first booting operation is a booting operation performed when the nonvolatile memory system is first powered on after mounted on a printed circuit board. The reprogramming is a program operation performed on the data stored in the second area without performing an erasing operation on the data stored in the second area.
1. An operating method of a nonvolatile memory system including first and second areas comprising:
storing data in the first area;
migrating data stored in the first area to the second area in a first booting operation; and
reprogramming the data stored in the second area,
wherein the first booting operation is performed upon the nonvolatile memory system being first powered on after mounted on a printed circuit board, and
wherein the reprogramming is a program operation performed on the data stored in the second area without performing an erasing operation on the data stored in the second area.
2. The operating method of claim 1 ,
wherein the storing of the data is performed before the nonvolatile memory system is mounted on the printed circuit board,
wherein the data stored in the first area is written on the basis of a first programming scheme, and
wherein the migrating of the data comprises:
reading the data stored in the first area from the first area; and
writing the data read from the first area to the second area on the basis of a second programming scheme.
3. The operating method of claim 2 ,
wherein the data stored in the first area includes an operating system image.
4. The operation method of claim 2 ,
wherein the first programming scheme is a single level cell programming scheme and the second programming scheme is a multi level cell programming scheme.
5. The operating method of claim 4 ,
wherein program verify voltages of the reprogram operation are the same as program verify voltages of the second programming scheme.
6. The operating method of claim 1 ,
wherein the reprogramming of the data comprises:
reading the data stored in the first area from the first area; and writing the data read from the first area to the second area,
wherein the migrating of data and the reprogramming of the data occur at the same memory cells of the second area.
7. The operating method of claim 1 ,
wherein the reprogramming of the data comprises:
reading the data stored in the second area from the second area; and
writing the data read from the second area to the second area, wherein the migrating of data and the reprogramming of the data occur at the same memory cells of the second area.
8. The operating method of claim 7 ,
wherein the reading of the data stored in the second area is performed using a plurality of read voltages controlled according to an elapsed time after the data is written to the second area.
9. The operating method of claim 1 ,
wherein the first and second areas comprise
a plurality of memory blocks, each memory block comprises a plurality of strings, and each string comprises a plurality of memory cells stacked in a direction perpendicular to a substrate, a string select transistor being disposed between the memory cells and a bit line; and
a ground select transistor being disposed between the memory cells and the substrate.
10. The operating method of claim 9 ,
wherein each memory cell is a charge trap flash (CTF) memory cell.
11. The operating method of claim 1 ,
wherein the migrating of the data is performed in response to an initial operation request received from an external device.
12. The operating method of claim 11 ,
wherein the reprogramming of the data is performed in response to a reprogramming request received from the external device.