Memory device and manufacturing method of the same

1. A memory device, comprising:

a substrate;

a 3D memory array comprising a first metal layer and a second metal layer disposed beneath the first metal layer, wherein a longitudinal direction of the first metal layer is perpendicular to a longitudinal direction of the second metal layer;

a periphery circuit stacked on the substrate, the periphery circuit comprising:

a patterned metal layer comprising a first portion and a second portion; and

a contact structure electrically connected to the patterned metal layer; and

a first conductive connection structure and a second conductive connection structure, each of the first conductive connection structure and the second conductive connection structure being respectively electrically connected to a corresponding one of the two portions of the patterned metal layer, wherein the 3D memory array is electrically connected to the periphery circuit via the first conductive connection structure and the second conductive connection structure, and the first metal layer is electrically connected to the periphery circuit via the first conductive connection structure, and the second metal layer is electrically connected to the periphery circuit via the second conductive connection structure.

2. The memory device according to claim 1 , wherein the periphery circuit further comprises a plurality of transistors electrically connected to the patterned metal layer via the contact structure.

3. The memory device according to claim 1 , wherein the 3D memory array is stacked on the periphery circuit.

4. The memory device according to claim 3 , further comprising:

an insulating layer disposed between the 3D memory array and the periphery circuit and covering the patterned metal layer.

5. The memory device according to claim 3 , wherein the patterned metal layer is disposed between the 3D memory array and the periphery circuit.

6. The memory device according to claim 1 , wherein the periphery circuit is stacked on the 3D memory array.

7. The memory device according to claim 6 , further comprising:

an epi-Si layer or a silicon-on-insulator (SOI) layer disposed between the 3D memory layer and the periphery circuit.

8. The memory device according to claim 1 , wherein the materials of the patterned metal layer and the contact structure independently comprise at least one of aluminum, copper, tungsten, or metal silicide, respectively.

9. The memory device according to claim 1 , wherein each of the first conductive connection structure and the second conductive connection structure has an aspect ratio of larger than 2.

10. A manufacturing method of a memory device, comprising:

providing a substrate;

disposing a 3D memory array and a periphery circuit stacked on the substrate, wherein the 3D memory array comprises a first metal layer and a second metal layer disposed beneath the first metal layer, a longitudinal direction of the first metal layer is perpendicular to a longitudinal direction of the second metal layer, and the periphery circuit comprises: a patterned metal layer comprising a first portion and a second portion; and a contact structure electrically connected to the patterned metal layer; and

forming a first conductive connection structure and a second conductive connection structure, each of the first conductive connection structure and the second conductive connection structure being respectively electrically connected to a corresponding one of the two portions of the patterned metal layer, wherein the 3D memory array is electrically connected to the periphery circuit via the first conductive connection structure and the second conductive connection structure, and the first metal layer is electrically connected to the periphery circuit via the first conductive connection structure, and the second metal layer is electrically connected to the periphery circuit via the second conductive connection structure.

11. The manufacturing method of the memory device according to claim 10 , wherein the periphery circuit further comprises a plurality of transistors electrically connected to the patterned metal layer via the contact structure.

12. The manufacturing method of the memory device according to claim 10 , wherein the step of disposing the 3D memory array and the periphery circuit stacked on the substrate comprises:

forming the periphery circuit on the substrate; and

stacking the 3D memory array on the periphery circuit.

13. The manufacturing method of the memory device according to claim 12 , further comprising:

disposing an insulating layer between the 3D memory array and the periphery circuit and covering the patterned metal layer.

14. The manufacturing method of the memory device according to claim 12 , wherein the patterned metal layer is disposed between the 3D memory array and the periphery circuit.

15. The manufacturing method of the memory device according to claim 10 , wherein the step of disposing the 3D memory array and the periphery circuit stacked on the substrate comprises:

forming the 3D memory array on the substrate; and

stacking the periphery circuit on the 3D memory array.

16. The manufacturing method of the memory device according to claim 15 , further comprising:

disposing an epi-Si layer or a SOI layer between the 3D memory array and the periphery circuit.

17. The manufacturing method of the memory device according to claim 10 , wherein the materials of the patterned metal layer and the contact structure independently comprise at least one of aluminum, copper, tungsten, or metal silicide, respectively.

18. The manufacturing method of the memory device according to claim 10 , wherein each of the conductive connection structure and the second conductive connection structure has an aspect ratio of larger than 2.