Semiconductor memory device and method for manufacturing same
According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.
1. A semiconductor device comprising:
first memory cells provided in a first stacked body including first electrode layers alternately stacked with a plurality of insulating layers therebetween, the first memory cells having the first electrode layers as control gates and a first semiconductor portion as channels extending inside the first stacked body;
second memory cells provided in a second stacked body including second electrode layers alternately stacked with a plurality of insulating layers therebetween, the second memory cells having the second electrode layers as control gates and a second semiconductor portion as channels extending inside the second stacked body; and
an interlayer cell having a conductive layer provided above the first stacked body and below the second stacked body and a third semiconductor portion provided between the first semiconductor portion and the second semiconductor portion, the interlayer cell and the first and second memory cells being connected in series via the first to third semiconductor portions, wherein
the interlayer cell is not used for storing data.
2. The device according to claim 1 , wherein
when programming of data is performed for a memory string including the first and second memory cells, a potential lower than a programming potential is applied to the intermediate layer.
3. The device according to claim 1 , wherein
the conductive layer includes a metal.
4. The device according to claim 3 , wherein
the conductive layer includes tungsten.
5. The device according to claim 1 , wherein
the conductive layer includes a material different from that of the first and second electrode layers.
6. The device according to claim 1 , wherein
the conductive layer includes a material same as that of the first and second electrode layers.
7. The device according to claim 1 , wherein
the second stacked body is stacked above the first stacked body via the conductive layer,
the first to third semiconductor portions are continuously formed in a hole piercing the first and second electrode layers and the conductive layer and extending in a stacking direction of the first and second stacked bodies.
8. The device according to claim 7 , wherein
a charge storage film is provided between the first semiconductor portion and the first electrode layers, between the second semiconductor portion and the second electrode layers, and between the third semiconductor portion and the conductive layer.
9. The device according to claim 8 , wherein
the charge storage film functions as a data storage layer of the first and second memory cells that store data.
10. The device according to claim 8 , wherein
programming of data is not performed for the charge storage film between the third semiconductor portion and the conductive layer.
11. The device according to claim 8 , wherein
the first and second electrode layers and the conductive layer are provided around outer circumferential surfaces of the first to third semiconductor portions.
12. The device according to claim 8 , wherein
a tunneling insulating film is provided between the charge storage film and the first to third semiconductor portions.
13. The device according to claim 7 , wherein
a lower end of a columnar member including the first to third semiconductor portions is connected to a source line and an upper end of the columnar member is connected to a bit line.
14. The device according to claim 13 , further comprising:
a first selection gate provided between the first stacked body and the source line and a second selection gate provided between the second stacked body and the bit line.
15. The device according to claim 13 , wherein
the columnar member includes a memory film provided around the first to third semiconductor portions.
16. The device according to claim 15 , wherein
the memory film includes a tunneling insulating film contacting the first to third semiconductor portions, a blocking insulating film contacting the first and second electrode layers and the conductive layer, and a charge storage film provided between the tunneling insulating film and the blocking insulating film.
17. The device according to claim 15 , wherein
the first to third semiconductor portions have a tubular configuration and the columnar member further includes an insulating film provided inside the first to third semiconductor portions.
18. A semiconductor memory device comprising:
a source-side selection gate;
first electrode layers provided above the source-side selection gate via a first insulating layer, the first electrode layers being alternately stacked with a plurality of insulating layers therebetween;
second electrode layers provided above the first electrode layers via an inter-electrode insulating layer, the second electrode layers being alternately stacked with a plurality of insulating layers therebetween;
a drain-side selection gate provided above the second electrode layers via a second insulating layer; and
an intermediate layer capable of being applied with a potential provided between the first electrode layers and the second electrode layers, wherein
the source-side selection gate controls a source-side selection transistor, the drain-side selection gate controls a drain-side selection transistor, the first electrode layers and the second electrode layers respectively control first memory cells and second memory cells both capable of storing data, and the intermediate layer controls a cell not used for storing data; and
the source-side selection transistor, the first memory cells, the cell not used for storing data, the second memory cells, and the drain-side selection transistor are connected in series via a semiconductor channel.
19. The device according to claim 18 , wherein
the source-side selection gate, the first electrode layers, the intermediate layer, the second electrode layers, and the drain-side selection gate are sequentially stacked above a substrate in a direction orthogonal to a major surface of the substrate.
20. The device according to claim 19 , wherein
the semiconductor channel pierces the source-side selection gate, the first electrode layers, the intermediate layer, the second electrode layers, and the drain-side selection gate and extends in the direction orthogonal to the major surface of the substrate.