Processor power measurement
A system can include a processing core to execute machine readable instructions. The system can also include a memory accessible by the processor core. The memory can include preprogrammed test data that characterizes one of an impedance of a processor and a current output to the processor during execution of a test routine. The processor can include the processing core and the one of the impedance of the processor and the current output to the processor is based on a power measurement taken during execution of a test routine. The power measurement can be taken with a current sensor that is at least one of lossy or at least about 98% accurate.
1. A system comprising:
a processing core configured to execute machine readable instructions; and
memory accessible by the processing core, wherein the memory includes preprogrammed test data that characterizes one of an impedance of a processor and a current output to the processor during execution of a test routine, wherein the processor includes the processing core, wherein the one of the impedance of the processor and the current output to the processor is based on a power measurement taken during execution of the test routine, wherein the power measurement is taken used to generate a calibration factor used during normal operation of the system to generate an accurate processor current measurement without need for a lossy current sensor.
2. The system of claim 1 , wherein the memory comprises a plurality of registers embedded in the processor.
3. The system of claim 1 , wherein the test routine comprises a plurality of machine readable instructions programmed to control power usage by the processor during execution of the test routine.
4. The system of claim 3 , wherein the test routine causes the processor to ramp power usage over at test time period upon execution.
5. The system of claim 3 , wherein the test routine causes the processor to increment power usage according to a prescribed step size upon execution.
6. The system of claim 3 , wherein data identifying the test routine is stored in the preprogrammed test data.
7. The system of claim 1 , wherein the preprogrammed test data includes data characterizing a clock speed of the processor during execution of the test routine.
8. The system of claim 1 , wherein the power measurement is based on a measurement of voltage and current provided directly to the processor.
9. A system comprising:
a processing core configured to execute machine readable instructions; and
memory accessible by the processing core, wherein the memory includes preprogrammed test data that characterizes one of an impedance of a processor and a current output to the processor during execution of a test routine, wherein the processor includes the processing core, wherein the one of the impedance of the processor and the current output to the processor is based on a power measurement taken during execution of the test routine, wherein the power measurement is taken with a current sensor that is at least one of lossy or at least about 98% accurate, further comprising:
a voltage core regulator comprising a substantially lossless current sensor, the voltage core regulator being configured to:
provide power to the processor; and
output data that characterizes a real-time current output to the processor by the voltage core regulator, wherein the memory further comprises:
a power test configured to:
determine a calibration factor for the processor based on the test data and the real time current provided to the processor; and
determine a calibrated power consumed by the processor based on the calibration factor and the real-time current provided to the processor.
10. The system of claim 9 , wherein the power test is further configured to determine a real-time current provided to the processor based on the impedance of the processor and data provided from the voltage core regulator that characterizes a real-time voltage output to the processor by the voltage core regulator.
11. The system of claim 9 , wherein the power test is further configured to determine the calibration factor during execution of the test routine at the processor.
12. The system of claim 9 , wherein the voltage core regulator is coupled to a power supply, the system further comprising:
a voltage regulator coupled to the power supply; and
a point of load (POL) configured to receive power from the voltage regulator, wherein the voltage regulator is configured to output data characterizing a real-time current measurement of current output to the POL;
wherein the power test is further configured to determine the calibration factor for the POL that characterizes a deviation between the real-time current measurement and a current provided to the POL during execution of a task routine, wherein the calibration factor is determined during execution of the task routine, wherein the task routine comprises one of a series of instructions executed by the POL and a series of instructions executed by the processor that cause the POL to operate in a predictable manner.
13. The system of claim 12 , wherein the POL comprises one of an analog circuit and a graphical processing unit.
14. The system of claim 12 , further comprising an input side current sensor configured to measure a current input into the voltage regulator.
15. A method comprising:
executing a test routine on a processor that executes machine readable instructions;
measuring, with a lossy current measuring device, a current provided to the processor during the test routine, wherein the test routine comprises a plurality of machine readable instructions;
storing test data that characterizes the measuring in a memory;
generating a calibration factor used during normal operation of the system generated accurate processor current measurement without need for a lossy current sensor.
16. The method of claim 15 , wherein the test data is stored in a register of the processor.
17. The method of claim 15 , wherein the test data comprises data that characterizes an impedance of the processor.
18. A data center comprising:
a plurality of computers that are each configured to store a power history, wherein a given power history of a given computer of the plurality of computers comprises a time-stamped instance of a calculated power consumed by the given computer;
wherein the calculated power is based on a real-time measured current provided to the given computer and a calibration factor;
wherein the calibration factor is based on test data characterizing one of an impedance of a processor of the given computer and a current provided to the processor of the given computer during execution of a test routine by the processor; and
a data center controller configured to adjust a workload assigned to each of the computers based on the power history of each of the computers.
19. The data center of claim 18 , wherein the data center controller is further configured to adjust an operating characteristic of a power supply coupled to the given computer based on the power history of the given computer.