Vertical channel-type 3D semiconductor memory device and method for manufacturing the same
A vertical channel-type 3D semiconductor memory device and a method for manufacturing the same are disclosed. In one aspect, the device includes a multi-layer film formed by depositing alternating layers of insulation and an electrode material on a substrate. The device also includes through-holes formed by etching the film to the substrate. The device also includes gate stacks formed by depositing barrier storage and a tunnel layers in sequence on inner walls of the through-holes. The device also includes hollow channels formed by depositing a channel material on the tunnel layer. The device also includes drains for bit-line connection in top portions of the hollow channels. The device also includes sources formed in contact regions between through-holes and the substrate in bottom portions of the hollow channels.
1. A vertical channel-type 3D semiconductor memory device, comprising:
a substrate;
a multi-layer film formed by depositing alternating layers of at least one insulating layer and at least one electrode material layer on the substrate;
a plurality of through-holes, which define respective channel regions, formed by etching the multi-layer film to the substrate;
a plurality of gate stacks, each formed by depositing a barrier layer, a storage layer, and a tunnel layer in sequence on an inner wall of a respective one of the plurality of through-holes;
a plurality of hollow channels, each formed by depositing and incompletely filling a channel material on a surface of the tunnel layer of a respective one of the plurality of gate stacks;
a plurality of drains, each formed in a contact hole region for bit-line connection in a top portion of a respective one of the plurality of hollow channels; and
a plurality of sources, each formed in a contact region between a respective one of the plurality of through-holes and the substrate in a bottom portion of a respective one of the plurality of hollow channels.
2. The device of claim 1 , wherein each of the plurality of hollow channels has a column, annular, or strip shape, and/or wherein the channel material is selected from the group consisting of polysilicon, amorphous silicon, Ge—Si, Ge, GaAs, and InGaAs.
3. The device of claim 2 ; wherein each of the plurality of hollow channels is formed by depositing a polysilicon film directly on the surface of a respective one of the tunnel layers.
4. The device of claim 2 , wherein each of the plurality of hollow channels is formed by depositing an amorphous silicon film on the surface of a respective one of the respective tunnel layers followed by high-temperature annealing.
5. The device of claim 1 , wherein each of the plurality of gate stacks is a charge capturing-type memory gate stack based on separate charge storage or a floating gate-type memory gate stack based on a continuous storage medium.
6. The device of claim 5 , wherein the charge capturing-type memory gate stack comprises:
a tunnel layer;
a separate dielectric storage layer; and
a barrier layer.
7. The device of claim 6 , wherein the separate dielectric storage layer comprises SiN or a high-K dielectric material of HfO.
8. The device of claim 5 , wherein the floating gate-type memory gate stack comprises:
a tunnel layer;
a storage layer; and
a barrier layer.
9. The device of claim 8 , wherein the storage layer comprises polysilicon, metal, or a combination of polysilicon and metal.