IP Library Granted Patent US 9,442,886
Granted Patent B2
US 9,442,886 · App. 14/848,334 · Granted Sep 13, 2016

Scheduling in a multicore architecture

Inventor: Mark David Lippett (Watlington, GB)
Assignees: Synopsys, Inc.; Fujitsu Semiconductor Limited
G06F15/80G06F1/3203G06F9/466G06F9/4893G06F9/5027G06F9/5038G06F2209/483G06F2209/5011Y02B60/144
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Quick Facts
Patent No.
US 9,442,886
App. No.
14/848,334
Filed
Sep 9, 2015
Granted
Sep 13, 2016
Kind
B2
Art Unit
2183
USPC
712/220
Abstract

This invention relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue.

Claims (47)

1. A method of scheduling executable transactions in a multicore processor comprising a plurality of processor elements, wherein at least one processor element comprises reconfigurable logic, the method comprising:

providing a first configuration queue of executable transactions allocated for execution by a first configuration of the reconfigurable logic and a second configuration queue of executable transactions allocated for execution by a second configuration of the reconfigurable logic;

providing a multilevel scheduler comprising a plurality of executable transaction schedulers each configured to determine a most eligible executable transaction for execution from a plurality of candidate executable transactions, each candidate executable transaction associated with the first configuration of the reconfigurable logic or the second configuration of the reconfigurable logic, the multilevel scheduler configured to:

output a determined most eligible executable transaction to the first configuration queue in response to the determined most eligible executable transaction being associated with the first configuration of the reconfigurable logic; and

output the determined most eligible executable transaction to the second configuration queue in response to the determined most eligible executable transaction being associated with the second configuration of the reconfigurable logic; and

when the reconfigurable logic is configured in the first configuration:

outputting executable transactions from the first configuration queue to the reconfiguration logic; and

reconfiguring the reconfigurable logic to the second configuration when a pre-determined threshold is reached.

2. The method of claim 1 , wherein reconfiguring the reconfigurable logic comprises:

stopping the output of the contents from the first configuration queue to the reconfigurable logic before reconfiguring the reconfigurable logic to the second configuration.

3. The method of claim 1 , wherein the pre-determined threshold is a maximum time allowed before a particular executable transaction must be executed.

4. The method of claim 1 , wherein the pre-determined threshold is a threshold number of transactions executed by the configurable logic when the reconfigurable logic is configured in the first configuration.

5. The method of claim 1 , wherein the pre-determined threshold is a threshold number of transactions in the second configuration queue.

6. The method of claim 1 , wherein the second configuration is selected from a plurality of configurations based on a length of the second configuration queue.

7. The method of claim 6 , wherein the second configuration is selected from a plurality of configurations in response to the second configuration queue being the longest configuration queue from among a plurality of configuration queues.

8. A non-transitory computer-readable storage medium comprising computer-executable instructions for scheduling executable transactions in a multicore processor comprising a plurality of processor elements, wherein at least one processor element comprises reconfigurable logic, the instructions, when executed, configured to:

provide a first configuration queue of executable transactions allocated for execution by a first configuration of the reconfigurable logic and a second configuration queue of executable transactions allocated for execution by a second configuration of the reconfigurable logic;

provide a multilevel scheduler comprising a plurality of executable transaction schedulers each configured to determine a most eligible executable transaction for execution from a plurality of candidate executable transactions, each candidate executable transaction associated with the first configuration of the reconfigurable logic or the second configuration of the reconfigurable logic, the multilevel scheduler configured to:

output a determined most eligible executable transaction to the first configuration queue in response to the determined most eligible executable transaction being associated with the first configuration of the reconfigurable logic; and

output the determined most eligible executable transaction to the second configuration queue in response to the determined most eligible executable transaction being associated with the second configuration of the reconfigurable logic; and

when the reconfigurable logic is configured in the first configuration:

output executable transactions from the first configuration queue to the reconfiguration logic; and

reconfigure the reconfigurable logic to the second configuration when a pre-determined threshold is reached.

9. The non-transitory computer-readable storage medium of claim 8 , wherein reconfiguring the reconfigurable logic comprises:

stopping the output of the contents from the first configuration queue to the reconfigurable logic before reconfiguring the reconfigurable logic to the second configuration.

10. The non-transitory computer-readable storage medium of claim 8 , wherein the pre-determined threshold is a maximum time allowed before a particular executable transaction must be executed.

11. The non-transitory computer-readable storage medium of claim 8 , wherein the pre-determined threshold is a threshold number of transactions executed by the configurable logic when the reconfigurable logic is configured in the first configuration.

12. The non-transitory computer-readable storage medium of claim 8 , wherein the pre-determined threshold is a threshold number of transactions in the second configuration queue.

13. The non-transitory computer-readable storage medium of claim 8 , wherein the second configuration is selected from a plurality of configurations based on a length of the second configuration queue.

14. The non-transitory computer-readable storage medium of claim 13 , wherein the second configuration is selected from a plurality of configurations in response to the second configuration queue being the longest configuration queue from among a plurality of configuration queues.

15. A multicore processor system comprising:

a multicore processor comprising a plurality of processor elements, where at least one processor element comprises reconfigurable logic;

a first configuration queue of executable transactions allocated for execution by a first configuration of the reconfigurable logic;

a second configuration queue of executable transactions allocated for execution by a second configuration of the reconfigurable logic;

a multilevel scheduler comprising a plurality of executable transaction schedulers each configured to determine a most eligible executable transaction for execution from a plurality of candidate executable transactions, each candidate executable transaction associated with the first configuration of the reconfigurable logic or the second configuration of the reconfigurable logic, the multilevel scheduler configured to:

output a determined most eligible executable transaction to the first configuration queue in response to the determined most eligible executable transaction being associated with the first configuration of the reconfigurable logic; and

output the determined most eligible executable transaction to the second configuration queue in response to the determined most eligible executable transaction being associated with the second configuration of the reconfigurable logic; and

a controller configured to, when the reconfigurable logic is configured in the first configuration:

output executable transactions from the first configuration queue to the reconfiguration logic; and

reconfigure the reconfigurable logic to the second configuration when a pre-determined threshold is reached.

16. The system of claim 15 , wherein reconfiguring the reconfigurable logic comprises:

stopping the output of the contents from the first configuration queue to the reconfigurable logic before reconfiguring the reconfigurable logic to the second configuration.

17. The system of claim 15 , wherein the pre-determined threshold is a maximum time allowed before a particular executable transaction must be executed.

18. The system of claim 15 , wherein the pre-determined threshold is a threshold number of transactions executed by the configurable logic when the reconfigurable logic is configured in the first configuration.

19. The system of claim 15 , wherein the pre-determined threshold is a threshold number of transactions in the second configuration queue.

20. The system of claim 15 , wherein the second configuration is selected from a plurality of configurations based on a length of the second configuration queue.

21. The system of claim 20 , wherein the second configuration is selected from a plurality of configurations in response to the second configuration queue being the longest configuration queue from among a plurality of configuration queues.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2018
From: LIPPETT, MARK DAVID
To: COWARE, INC.
Reel/Frame 046258/0701 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2018
From: COWARE, INC.
To: FUJITSU LIMITED
Reel/Frame 046258/0718 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2018
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 046258/0759 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2018
From: COWARE, LLC
To: SYNOPSYS, INC.
Reel/Frame 046258/0772 →
CHANGE OF NAME Recorded Jul 3, 2018
From: COWARE, INC.
To: COWARE, LLC
Reel/Frame 046473/0396 →
CHANGE OF NAME Recorded Jul 3, 2018
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 046473/0417 →
Priority Claims (1)
GB 20050019981.5 · Sep 30, 2005 · national
Continuity (4)
Continuation 14267830 · May 1, 2014
Division 13965124 · Aug 12, 2013
Continuation 11540146 · Sep 29, 2006
Related Publication 20150378776A1 · Dec 31, 2015