Method of making a FinFET device

1. A method for making an integrated circuit (IC), the method comprising:

providing a substrate having a first region and a second region;

forming a plurality of mandrel features in the first region with a first spacing;

forming first spacers along sidewalls of the mandrel features with a targeted width A;

forming second spacers with a first width W 1 along sidewalls of the first spacers, wherein two back-to-back adjacent second spacers are separated by a gap;

depositing a dielectric material in the gap and in the second region;

performing a first cut thereby removing a first subset of the first spacers; and

coincident with the removing of the first subset, partially removing the dielectric material in the second region thereby forming a mesa of the dielectric material in the second region.

2. The method of claim 1 , wherein a width of the gap is about the same as the targeted width A.

3. The method of claim 1 , wherein the first spacing is about equal to (2×W 1 ) +(3×A).

4. The method of claim 1 , wherein the mesa has a second width W 2 substantially larger than the first width W 1 .

5. The method of claim 1 , wherein the mandrel features each have a width about the same as W 1 .

6. The method of claim 1 , wherein the depositing of the dielectric material includes:

depositing the dielectric material over the substrate and filling in the gap; and

recessing the dielectric material to expose top surfaces of the mandrel features.

7. The method of claim 6 , wherein the recessing of the dielectric material is by a chemical mechanical polishing (CMP) process.

8. The method of claim 1 , wherein the removing of the first subset and the partially removing of the dielectric material are performed with the same cut pattern.

9. The method of claim 1 , further comprising:

removing the mandrel features and the second spacers; and

etching the substrate using at least a portion of the first spacers and the mesa as an etch mask.

10. The method of claim 9 , further comprising:

after the etching of the substrate, forming a second cut pattern with openings to expose a second subset of the first spacers; and

performing a second cut to remove the second subset of the first spacers to form an isolation trench in the substrate.

11. The method of claim 10 , wherein the second cut is in a direction which is perpendicular to the first cut.

12. The method of claim 1 , wherein the first spacers and the dielectric material are of the same material.

13. The method of claim 1 , wherein the second spacers and the mandrel features are of the same dielectric material that is different from the first spacer material.

14. A method for fabricating a fin-type field-effect transistor (FinFET) device, the method comprising:

providing a substrate having a first region and a second region;

forming a plurality of mandrel features in the first region with a first spacing;

forming first spacers along sidewalls of the mandrel features with a targeted width A;

forming second spacers with a first width W 1 along sidewalls of the first spacer, wherein two back-to-back adjacent second spacers are separate by a gap;

forming a first dielectric feature in the gap and a second dielectric feature in the second region;

performing a first cut thereby removing a first subset of the first spacers;

coincident with the removing of the first subset, removing a portion of the second dielectric feature thereby forming a dielectric mesa with a second width W 2 in the second region, wherein the second width W 2 is substantially larger than the first width W 1 ;

removing the mandrel features and the second spacers;

etching the substrate using at least a portion of the first spacers and the first dielectric feature as an etch mask to form fins; and

coincident with the etching of the substrate to form fins, etching the substrate using the mesa as an etch mask to form a substrate mesa.

15. The method of claim 14 , further comprising:

performing a second cut to remove a subset of the fins to form an isolation trench, wherein the second cut is in a direction which is perpendicular to the first cut.

16. The method of claim 14 , wherein:

the mandrel features and the second spacers are of a first material; and

the first spacers and the first and second dielectric features are of a second material that is different from the first material.

17. The method of claim 14 , wherein:

a width of the gap is about the same as the targeted width A;

the first spacing is about equal to (2×W 1 )+(3×A); and

the mandrel features each have a width about the same as W 1 .

18. A method for integrated circuit (IC), comprising:

providing a substrate having a first region and a second region;

forming mandrel features in the first region;

forming first spacers on sidewalls of the mandrel feature;

forming second spacers on sidewalls of the first spacer such that two adjacent second spacers are separated by a gap having the same width as the first spacer;

depositing a dielectric layer over the substrate, including fully filling in the gap;

recessing the dielectric layer to form a first dielectric feature in the gap and a second dielectric feature in the second region;

forming a patterned resist layer to expose a subset of the first spacer and a portion of the second dielectric layer;

etching through the patterned resist layer to remove the subset of the first spacer and the portion of the second dielectric layer thereby forming a dielectric mesa in the second region; and

removing the mandrel features and the second spacers.

19. The method of claim 18 , further comprising:

etching the substrate using a portion of the first spacers, the first dielectric feature, and the mesa as an etch mask.

20. The method of claim 18 , wherein:

the mandrel features each have a width W 1 ;

the second spacers each have a width about W 1 ;

the gap has a width A; and

the mandrel features have a spacing S, wherein S is about equal to (2×W 1 )+(3×A).