Arrangement for plasma processing system control based on RF voltage

1. An arrangement for controlling a plasma processing system that includes a plasma processing chamber, the arrangement comprising:

a radio frequency (RF) sensing mechanism, said RF sensing mechanism is proximate to a non-plasma exposing component of an electrostatic chuck (ESC) disposed within the plasma processing system, to obtain an RF voltage signal;

a voltage probe coupled to said RF sensing mechanism to facilitate acquisition of said RF voltage signal while reducing perturbation of RF power driving a plasma in said plasma processing system;

a signal processing arrangement including,

an anti-aliasing filter to filter RF voltage signal received from the voltage probe;

a RF splitter to split the filtered RF voltage signal into a plurality of channels and to convert the RF voltage signal for each of the plurality of channels into a corresponding direct current (DC) signal;

an analog-to-digital converter (ADC) to convert the DC signal of each of the plurality of channels in a digital domain to a corresponding digital signal;

a digital processing block to process the digital signals within the digital domain, wherein the process includes,

(a) maintaining one of the digital signals as an unfiltered broadband version of the digital signal;

(b) filtering the digital signals, wherein the filtering includes detecting a peak voltage of each frequency of the plurality of channels and peak voltage of a composite broadband signal;

(c) calibrating each of the plurality of digital signals;

(d) computing a transfer function using the digital signals as input to obtain a transfer function output, the transfer function output accounting for contribution of frequency of each of the plurality of channels of the RF voltage signal in wafer bias; and

an ESC power supply subsystem configured to receive said transfer function output as a feedback signal to control said plasma processing system.

2. The arrangement of claim 1 , wherein detecting peak voltage includes detecting one of a positive peak voltage, a negative peak voltage, or a combination of both the positive peak voltage and the negative peak voltage.

3. The arrangement of claim 1 , wherein the ADC is a multi-channel ADC.

4. The arrangement of claim 1 , wherein the non-plasma exposing component is a base plate.

5. The arrangement of claim 1 , wherein the RF sensing mechanism is an RF rod.

6. The arrangement of claim 1 , wherein the voltage probe is implemented at least by a capacitor divider network.

7. The arrangement of claim 1 , wherein the transfer function represents a linear transfer function.

8. The arrangement of claim 1 , wherein the transfer function represents a non-linear transfer function.

9. The arrangement of claim 1 , wherein a filter frequency of the anti-aliasing low-pass filter is set to half of a sampling rate of the ADC.

10. The arrangement of claim 1 wherein said processing in the digital domain is performed by a field programmable gate array (FPGA).

11. The arrangement of claim 1 , wherein computing the transfer function further includes using at least one plasma processing chamber parameter to generate the transfer function output that affects wafer bias.

12. The arrangement of claim 1 , wherein the plasma processing chamber parameter includes at least one of chamber pressure, chamber gap defined by distance between electrodes, RF delivered power, RF frequency, RF generator impedance matching network tap positions having capacitor positions of variable inductance-capacitance (LC) network, chamber chemistry, chamber topology including a ground area ratio, wafer type, and wafer resistivity.