Method and apparatus for mitigating parasitic coupling in a packaged integrated circuit
A packaged IC has a package with a die paddle, a signal lead, and a ground lead. The packaged IC also has a die, secured to the package, with a ground pad and a signal pad. The signal pad is electrically connected to the signal lead, and the ground pad is electrically connected to both the die paddle and the ground lead.
1. A packaged IC comprising:
a package having a die paddle, a signal lead, and a ground lead; and
a die having a ground pad and a signal pad, the die being secured to the package;
the signal pad being electrically connected to the signal lead,
the ground pad being electrically connected to both the die paddle and the ground lead, wherein the die comprises a via extending from the ground pad, the via being electrically connected with the die paddle.
2. The packaged IC as defined by claim 1 wherein the die comprises a CMOS, SOI (silicon-on-insulator) CMOS, or silicon-germanium BiCMOS substrate.
3. The packaged IC as defined by claim 1 wherein the die has a top side and a back side, the top side including the ground pad and the signal pad, the back side including back side die metal in contact with the ground pad through the via, the back side die metal being electrically connected with the die paddle.
4. The packaged IC as defined by claim 1 further comprising a wirebond connecting the ground pad to the ground lead.
5. The packaged IC as defined by claim 1 further comprising a first wirebond connected between the ground pad and the ground lead, the first wirebond physically connecting the ground pad with the ground lead, the packaged IC further comprising a second wirebond connected between the ground pad and the die paddle, the second wirebond electrically connecting the ground pad with the die paddle.
6. The packaged IC as defined by claim 1 wherein the package comprises a leadframe package.
7. The packaged IC as defined by claim 1 wherein the die paddle and ground pad are configured to be at a ground potential when energized.
8. The packaged IC as defined by claim 1 wherein the die comprises a phased array configured to operate at frequencies of between about 1 Megahertz and 100 Gigahertz.
9. The packaged IC as defined by claim 1 wherein the die has a second ground pad, the package having a second ground lead, the second ground pad being electrically connected to both the die paddle and the second ground lead.
10. The packaged IC as defined by claim 9 wherein the signal lead is positioned between the ground lead and the second ground lead.
11. A packaged IC comprising:
a phased array die having a plurality of die RF groups, each die RF group comprising a first ground pad, a signal pad, and a second ground pad;
a package having a die paddle and a plurality of package RF groups, each package RF group comprising a first ground lead, a signal lead, and a second ground lead; and
a plurality of connectors connecting a given die RF group with a given package RF group, the given die RF group having given first and second ground pads and a given signal pad, the given package RF group having given first and second ground leads and a given signal lead,
the plurality of connectors comprising a first connector, a second connector, and a third connector, the first connector connecting the given first ground pad to the given first ground lead, the second connector connecting the given second ground pad to the given second ground lead, and the third connector connecting the given signal pad to the given signal lead,
the plurality of connectors also having a first paddle connector connecting the given first ground pad to the die paddle, wherein the first paddle connector comprises a via extending from the given first ground pad,
the plurality of connectors further having a second paddle connector connecting the given second ground pad to the die paddle.
12. The packaged IC as defined by claim 11 wherein the given signal lead is positioned between the first and second ground leads.
13. The packaged IC as defined by claim 11 wherein the second paddle connector comprises a via extending from the given second ground pad.
14. The packaged IC as defined by claim 11 wherein the first paddle connector comprises a first wirebond.
15. The packaged IC as defined by claim 14 wherein the second paddle connector comprises a second wirebond extending from the given second ground pad.
16. The packaged IC as defined by claim 11 wherein the package comprises a leadframe package.
17. The packaged IC as defined by claim 11 wherein the phased array die operates at frequencies of between about 1 Megahertz and 100 Gigahertz.
18. The packaged IC as defined by claim 11 wherein the die comprises a CMOS, SOI (silicon-on-insulator) CMOS, or silicon-germanium BiCMOS substrate.
19. A method of forming a packaged IC, the method comprising:
providing a die having a ground pad and a signal pad;
providing a leadframe base having a die paddle, a ground lead, and a signal lead;
electrically connecting the signal pad of the die with the signal lead of the leadframe base;
electrically connecting the ground pad of the die with the ground lead of the leadframe base;
electrically connecting the ground pad of the die with the die paddle of the leadframe base;
encapsulating the die and at least part of the leadframe base; and wherein the die comprises a via extending from the ground pad, electrically connecting the ground pad of the die with the die paddle comprising electrically connecting the via with the die paddle.
20. The method as defined by claim 19 wherein electrically connecting the ground pad of the die with the die paddle comprises securing the die to the leadframe.
21. The method as defined by claim 19 wherein electrically connecting the ground pad of the die with the die paddle of the leadframe base comprises connecting a wirebond between the ground pad of the die and the die paddle.