IP Library Granted Patent US 9,455,299
Granted Patent B2
US 9,455,299 · App. 14/755,665 · Granted Sep 27, 2016

Methods for semiconductor sensor structures with reduced dislocation defect densities

Inventors: Zhiyuan Cheng (Lincoln, MA); James Fiorenza (Wilmington, MA); Calvin Sheen (Derry, NH); Anthony J. Lochtefeld (Ipswich, MA)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L27/14689H01L21/02532H01L27/1446H01L27/14612H01L27/14643H01L31/0304H01L31/0312H01L31/03046H01L31/103H01L31/105H01L31/1037H01L21/02381H01L21/02521H01L21/02639H01L21/02647H01L21/76224Y02E10/544
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Quick Facts
Patent No.
US 9,455,299
App. No.
14/755,665
Granted
Sep 27, 2016
Kind
B2
Abstract

Non-silicon based semiconductor devices are integrated into silicon fabrication processes by using aspect-ratio-trapping materials. Non-silicon light-sensing devices in a least a portion of a crystalline material can output electrons generated by light absorption therein. Exemplary light-sensing devices can have relatively large micron dimensions. As an exemplary application, complementary-metal-oxide-semiconductor photodetectors are formed on a silicon substrate by incorporating an aspect-ratio-trapping technique.

Claims (37)

1. A method comprising:

converting received light into a voltage signal by a sensor, the sensor being disposed in a first crystalline material, the first crystalline material being in a recess in a substrate, the recess having non-crystalline sidewalls, the substrate comprising a second crystalline material lattice mismatched to the first crystalline material; and

amplifying the voltage signal into an amplified signal using a first transistor, the first transistor comprising a first source/drain region disposed in the second crystalline material.

2. The method of claim 1 , wherein the sensor comprises a p-n junction in the first crystalline material.

3. The method of claim 1 , wherein the sensor comprises a p-i-n structure in the first crystalline material.

4. The method of claim 1 further comprising reading out the amplified signal comprising selectively applying a column signal to a second transistor and a row signal to a third transistor, the second transistor having a second source/drain region disposed in the second crystalline material, the third transistor having a third source/drain region disposed in the second crystalline material.

5. The method of claim 1 , wherein a dielectric material is disposed along a bottom surface of the recess, an opening being defined through the dielectric material to the bottom surface of the recess, the first crystalline material being disposed at least partially in the opening.

6. The method of claim 1 , wherein a dielectric material is disposed along a bottom surface of the recess, a plurality of openings being defined through the dielectric material to the bottom surface of the recess, the first crystalline material being disposed at least partially in each of the plurality of openings.

7. The method of claim 1 , wherein the first crystalline material comprises defects arising from lattice-mismatch to the second crystalline material, a majority of the defects being trapped at the non-crystalline sidewalls.

8. The method of claim 1 , wherein a graded buffer material is disposed in the recess, the first crystalline material being disposed on the graded buffer material.

9. A method comprising:

forming a recess in a first crystalline material of a substrate;

forming a first non-crystalline material along sidewalls of the recess;

epitaxially growing a second crystalline material in the recess, the second crystalline material being lattice mismatched to the first crystalline material, the second crystalline material comprising defects arising from the lattice-mismatch to the first crystalline material in a lower portion of the recess, the second crystalline material in an upper portion of the recess being substantially free from defects;

forming a photodetector in the second crystalline material; and

forming a transistor at least partially in the first crystalline material.

10. The method of claim 9 , wherein the photodetector comprises a lateral p-n junction in the second crystalline material.

11. The method of claim 9 , wherein the photodetector comprises a lateral p-i-n structure in the second crystalline material.

12. The method of claim 9 further comprising:

forming a second non-crystalline material along a bottom surface of the recess; and

defining an opening through the second non-crystalline material to the bottom surface of the recess, the second crystalline material being disposed at least partially in the opening.

13. The method of claim 9 further comprising:

forming a second non-crystalline material along a bottom surface of the recess; and

defining a plurality of openings through the second non-crystalline material to the bottom surface of the recess, the second crystalline material being disposed at least partially in each of the plurality of openings and coalescing over the first non-crystalline material.

14. The method of claim 9 further comprising forming a graded buffer material in the recess, the second crystalline material being formed on the graded buffer material.

15. The method of claim 9 , wherein a topmost surface of the photodetector extends above a topmost surface of the first crystalline material of the substrate.

16. A method comprising:

forming a trench with non-crystalline sidewalls on a first crystalline material of a substrate;

epitaxially growing a second crystalline material lattice mismatched to the first crystalline material in the trench, a lower portion of the second crystalline material in the trench having defects arising from the lattice mismatch to the first crystalline material, an upper portion of the second crystalline material in the trench being substantially free from defects arising from the lattice mismatch;

forming a p-region in the upper portion of the second crystalline material, the p-region extending from an upper surface of the second crystalline material into the second crystalline material; and

forming an n-region in the upper portion of the second crystalline material, the n-region extending from the upper surface of the second crystalline material into the second crystalline material.

17. The method of claim 16 , wherein an intrinsic region of the second crystalline material is disposed between the p-region and the n-region.

18. The method of claim 16 further comprising:

forming a first contact to the p-region, the first contact being on the upper surface of the second crystalline material; and

forming a second contact to the n-region, the first contact being on the upper surface of the second crystalline material.

19. The method of claim 16 , wherein the trench is formed in a non-crystalline layer over the substrate.

20. The method of claim 16 , wherein the trench is formed in the first crystalline material of the substrate, a non-crystalline material being formed along sidewalls of the trench to form the non-crystalline sidewalls.

Continuity (5)
Continuation 14333204 · Jul 16, 2014
Continuation 13594519 · Aug 24, 2012
Division 12565863 · Sep 24, 2009
Provisional Application 61099902 · Sep 24, 2008
Related Publication 20150325619A1 · Nov 12, 2015