Error injection and error counting during memory scrubbing operations
Embodiments relate to performing a memory scrubbing operation that includes injecting an error on a write operation associated with a memory address. One or more errors are detected during a two-pass scrub operation on the memory address. Based on a result of the two-pass scrub operation, one or more of a hard error counter associated with the memory address and a soft error counter associated with the memory address is selected. The one or more selected counters are updated based on the result of the two-pass scrub operation.
1. A computer program product for injecting errors during a memory operation, the computer program product comprising:
a computer readable storage medium having program instructions embodied therewith, the program instructions readable by a processing circuit to cause the processing circuit to perform a method comprising:
injecting an error to test error count thresholds, the injecting on a write operation associated with a memory address;
detecting one or more errors during a two-pass scrub operation on the memory address;
selecting, based on a result of the two-pass scrub operation, one or more of a hard error counter associated with the memory address and a soft error counter associated with the memory address; and
updating the one or more selected counters based on the result of the two-pass scrub operation.
2. The computer program product of claim 1 , wherein the method further comprises:
correcting the one or more errors detected during the two-pass scrub operation.
3. The computer program product of claim 1 , wherein the method further comprises:
re-injecting the one or more errors detected during the two-pass scrub operation.
4. The computer program product of claim 1 , wherein the method further comprises:
selecting one or more store types based on reading a field in a configuration register; and
injecting the error only for the one or more selected store types.
5. The computer program product of claim 1 , wherein the method further comprises:
selecting a memory domain based on reading a field in a configuration register; and
injecting the error only for the selected memory domain.
6. The computer program product of claim 1 , wherein the method further comprises:
selecting one or more memory ranks based on reading a field in a configuration register; and
injecting the error only for the one or more selected memory ranks.
7. The computer program product of claim 1 , wherein the method further comprises:
setting an injection limit by reading a count field in a configuration register; and
injecting a number of errors equal to the injection limit.
8. The computer program product of claim 1 , wherein the performing the two-pass scrub operation further includes performing a patrol fetch at the memory address and performing a store-back at the memory address, wherein the injecting the error occurs during the store-back.
9. A memory system for performing a scrub operation, the memory system comprising:
a memory controller; and
a plurality of memory modules in communication with the memory controller;
the memory system configured to perform a method comprising:
injecting an error to test error count thresholds, the injecting on a write operation associated with a memory address;
detecting one or more errors during a two-pass scrub operation on the memory address;
selecting, based on a result of the two-pass scrub operation, one or more of a hard error counter associated with the memory address and a soft error counter associated with the memory address; and
updating the one or more selected counters based on the result of the two-pass scrub operation.
10. The memory system of claim 9 , the method further comprising:
selecting one or more store types based on reading a field in a configuration register; and
injecting the error only for the one or more selected store types.
11. The memory system of claim 9 , the method further comprising:
selecting a memory domain based on reading a field in a configuration register; and
injecting the error only for the selected memory domain.
12. The memory system of claim 9 , the method further comprising:
selecting one or more memory ranks based on reading a field in a configuration register; and
injecting the error only for the one or more selected memory ranks.
13. The memory system of claim 9 , the method further comprising:
setting an injection limit by reading a count field in a configuration register; and
injecting a number of errors equal to the injection limit.