IP Library Granted Patent US 9,460,928
Granted Patent B2
US 9,460,928 · App. 14/612,359 · Granted Oct 4, 2016

Method for manufacturing semiconductor devices

Inventors: Chen-Han Chou (Tainan, TW); I-Chen Yang (Changhua, TW); Yao-Wen Chang (Hsinchu, TW); Tao-Cheng Lu (Hsinchu, TW)
Assignee: Macronix International Co., Ltd.
H01L21/26586H01L21/8232H01L22/20H01L27/11521H01L27/11568H01L29/167
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,460,928
App. No.
14/612,359
Granted
Oct 4, 2016
Kind
B2
Abstract

A semiconductor device manufacturing method includes preparing a wafer having projections formed on a substrate. The projections project upward from a surface of the substrate and have a height measured from the surface of the substrate. The method further includes determining an interval distribution representing a distribution of intervals between neighboring projections and calculating an implantation angle based on the height and the interval distribution. The implantation angle is an angle between a normal direction of the substrate and an implantation direction. The method also includes implanting ions at the calculated implantation angle.

Claims (13)

1. A semiconductor device comprising:

a substrate;

a plurality of projections formed on the substrate, the projections projecting upward from a surface of the substrate, the projections being arranged at a same pitch, and intervals between neighboring projections being different from each other; and

a plurality of doped regions formed in the substrate and between the projections, the doped regions corresponding to the intervals and having different doping levels.

2. The semiconductor device of claim 1 , wherein the doping levels in the doped regions are proportional to the intervals.

3. The semiconductor device of claim 1 , wherein the projections have approximately same heights.

4. The semiconductor device of claim 1 , wherein the projections include gate structures of transistors.

5. The semiconductor device of claim 1 , wherein the projections belong to a patterned layer.

6. The semiconductor device of claim 5 , wherein the patterned layer includes a patterned layer of a single material.

7. The semiconductor device of claim 5 , wherein the patterned layer includes a patterned layer of stacked materials.

8. The semiconductor device of claim 1 , wherein the projections are arranged along a word-line direction of the device.

9. The semiconductor device of claim 1 , wherein the projections are arranged along a bit-line direction of the device.

10. The semiconductor device of claim 1 , wherein the doped regions are doped with at least one of arsenic ions, boron ions, indium ions, antimony ions, nitrogen ions, germanium ions, carbon ions, or phosphorus ions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2015
From: CHOU, CHEN-HAN; YANG, I-CHEN; CHANG, YAO-WEN; LU, TAO-CHENG
To: MACRONIX INTERNATIONAL CO., LTD.
Reel/Frame 034872/0399 →
Continuity (1)
Related Publication 20160225627A1 · Aug 4, 2016