IP Library Granted Patent US 9,461,667
Granted Patent B2
US 9,461,667 · App. 14/243,568 · Granted Oct 4, 2016

Rounding injection scheme for floating-point to integer conversion

Inventor: Eric C. Quinnell (Austin, TX)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H03M7/24
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Quick Facts
Patent No.
US 9,461,667
App. No.
14/243,568
Granted
Oct 4, 2016
Kind
B2
Abstract

According to one general aspect, an apparatus may include a memory, a normalization engine, a lookup table, and an adder. The memory may be configured to store a floating-point number formatted in a floating-point format. The normalization engine may be configured to normalize at least a portion of the floating-point number to create a normalized number. The lookup table may be configured to generate an injection constant based upon a predefined set of rounding values specifically for converting a floating-point number to an integer number. The adder may be configured to create an integer result by adding the normalized number and the injection constant.

Claims (52)

1. An apparatus comprising:

a memory configured to store a floating point number formatted in a floating point format;

a normalization engine configured to normalize at least a portion of the floating point number to create a normalized number;

a lookup table configured to generate an injection constant based upon a rounding mode for converting a floating-point number to an integer number; and

an adder configured to create an integer result by adding the normalized number and the injection constant.

2. The apparatus of claim 1 , wherein the adder is configured to only add the normalized number and the injection constant.

3. The apparatus of claim 1 , wherein the injection constant comprises a round injection bit, a sticky injection bit, and a carry-in value.

4. The apparatus of claim 1 , wherein the injection constant comprises:

a carry in bit equal to a sign bit of the floating point number; and

if instructed to round to zero, a round injection bit and a sticky injection bit both equal to the sign bit of the floating point number,

if instructed to round to minus infinity, a round injection bit and a sticky injection bit both equal to zero,

if instructed to round to positive infinity, a round injection bit and a sticky injection bit both equal to one, and

if instructed to round to a nearest even value, a round injection bit equal to one and a sticky injection bit equal to zero.

5. The apparatus of claim 1 , wherein the normalization engine is configured to, if the floating point number is negative, invert, via a one's complement, a normalized version of the floating point number.

6. The apparatus of claim 1 , further comprising:

a least-significant bit correction circuit configured to determine if a least-significant bit of the integer result is to be corrected, wherein the determination is based in part upon the predefined set of injection constants.

7. The apparatus of claim 1 , wherein the integer result comprises an integer value formatted in a two's complement format.

8. The apparatus of claim 1 , wherein the integer result comprises an integer value in an unsigned format.

9. A method comprising

receiving a floating point number formatted in a floating point format;

normalizing at least a portion of the floating point number to create a normalized number;

calculating at least one rounding value according to a rounding mode for converting a floating-point number to an integer number; and

adding the normalized number and the rounding value to create an integer result.

10. The method of claim 9 , wherein adding the normalized number and the rounding value to create an integer result comprises adding only the normalized number with the rounding value.

11. The method of claim 9 , wherein the at least one rounding value comprises a rounding injection bit, a sticky injection bit, and a carry-in value.

12. The method of claim 9 , wherein the at least one rounding value comprises:

a carry in bit equal to a sign bit of the floating point number; and

if instructed to round to zero, a round injection bit and a sticky injection bit both equal to the sign bit of the floating point number,

if instructed to round to minus infinity, a round injection bit and a sticky injection bit both equal to zero,

if instructed to round to positive infinity, a round injection bit and a sticky injection bit both equal to one, and

if instructed to round to a nearest even value, a round injection bit equal to one and a sticky injection bit equal to zero.

13. The method of claim 9 , wherein normalizing at least a portion of the floating point number comprises:

if the floating point number is negative, inverting, via a one's complement, a normalized version of the floating point number.

14. The method of claim 9 , further comprising:

determining if a least-significant bit of the integer result is to be corrected, wherein the determination is based in part upon the rounding mode, and

if so, correcting the least-significant bit of the integer result.

15. The method of claim 9 , wherein the integer result comprises an integer value formatted in a two's complement format.

16. The method of claim 9 , wherein the integer result comprises an integer value in an unsigned format.

17. A system comprising:

a memory configured to store a floating point number formatted in a floating point format; and

a floating-point conversion unit configured to convert a floating point number to an integer number and comprising:

a normalization engine configured to normalize at least a portion of the floating point number to create a normalized number,

a lookup table configured to generate an injection constant based upon a rounding mode for converting a floating-point number to an integer number, and

an adder configured to create an integer result by adding the normalized number and the injection constant.

18. The system of claim 17 , wherein the adder is configured to only add the normalized number and the injection constant.

19. The system of claim 17 , wherein the injection constant comprises:

a carry in bit equal to a sign bit of the floating point number; and

if instructed to round to zero, a round injection bit and a sticky injection bit both equal to the sign bit of the floating point number,

if instructed to round to minus infinity, a round injection bit and a sticky injection bit both equal to zero,

if instructed to round to positive infinity, a round injection bit and a sticky injection bit both equal to one, and

if instructed to round to a nearest even value, a round injection bit equal to one and a sticky injection bit equal to zero.

20. The system of claim 17 , wherein the integer result comprises an integer value formatted in a two's complement format.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 2, 2014
From: QUINNELL, ERIC C.
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 032585/0810 →
Continuity (2)
Provisional Application 61922081 · Dec 30, 2013
Related Publication 20150186111A1 · Jul 2, 2015