Liquid discharge substrate, liquid discharge head, and recording device

1. A liquid discharge substrate comprising:

a plurality of discharge elements;

a first transistor configured to form a common electric path with respect to the plurality of discharge elements; and

a plurality of second transistors configured to be controlled independently from each other, wherein

an electric path is formed from a first power supply node to a second power supply node in an order of the first transistor, one of the plurality of discharge elements, and one of the plurality of second transistors so that the plurality of discharge elements are driven by the plurality of second transistors independently from each other, and

the first transistor is disposed between the plurality of discharge elements and the plurality of second transistors.

2. The liquid discharge substrate according to claim 1 , wherein an effective channel width Wc and an effective channel length Lc of the first transistor, and an effective channel width Wi and an effective channel length Li of the second transistor satisfy an expression (1):

Wc/Lc>Wi/Li   (1).

3. The liquid discharge substrate according to claim 1 , comprising:

a first wiring extending along a first direction in which the plurality of discharge elements are arranged, and forming the first power supply node; and

a second wiring extending along the first direction and forming the second power supply node, wherein

the first wiring is disposed between the plurality of discharge elements and the second wiring as viewed in plan.

4. The liquid discharge substrate according to claim 3 , wherein a width W 1 of the first wiring along a second direction intersecting the first direction is smaller than a width W 2 of the second wiring along the second direction.

5. The liquid discharge substrate according to claim 1 , comprising a control unit configured to control the plurality of second transistors independently from each other, wherein

the first transistor and the plurality of second transistors are disposed between the plurality of discharge elements and the control unit.

6. The liquid discharge substrate according to claim 1 , wherein

the first transistor includes a plurality of first MOS transistors arranged along a direction in which the plurality of discharge elements are arranged,

gates of the plurality of first MOS transistors are mutually connected,

sources of the plurality of first MOS transistors are mutually connected, and

drains of the plurality of first MOS transistors are mutually connected.

7. The liquid discharge substrate according to claim 6 , comprising a connection wire electrically connecting one of the plurality of second transistors and one of the plurality of discharge elements, wherein

the connection wire extends along a direction intersecting the direction in which the plurality of discharge elements are arranged, and includes a portion disposed between adjacent two of the plurality of first MOS transistors as viewed in plan.

8. The liquid discharge substrate according to claim 7 , wherein adjacent two of the plurality of first MOS transistors are respectively disposed in two different active regions.

9. The liquid discharge substrate according to claim 6 , wherein any two of the plurality of first MOS transistors share a semiconductor region forming the source or drain.

10. The liquid discharge substrate according to claim 6 , wherein a channel direction of the plurality of first MOS transistors is along the direction in which the plurality of discharge elements are arranged.

11. The liquid discharge substrate according to claim 1 , wherein

each of the plurality of second transistors includes a plurality of second MOS transistors arranged along a direction in which the plurality of discharge elements are arranged,

gates of the plurality of second MOS transistors are mutually connected,

sources of the plurality of second MOS transistors are mutually connected, and

drains of the plurality of second MOS transistors are mutually connected.

12. The liquid discharge substrate according to claim 11 , wherein any two of the plurality of second MOS transistors share a semiconductor region forming the source or drain.

13. The liquid discharge substrate according to claim 11 , wherein a channel direction of the plurality of second MOS transistors is along the direction in which the plurality of discharge elements are arranged.

14. The liquid discharge substrate according to claim 1 , wherein the plurality of second MOS transistors are disposed in one active region.

15. A liquid discharge head comprising:

the liquid discharge substrate according to claim 1 ; and

a liquid supply unit configured to supply a liquid to the liquid discharge substrate.

16. A recording device comprising:

the liquid discharge head according to claim 15 ; and

a drive unit configured to drive the liquid discharge head.

17. A liquid discharge substrate comprising:

a plurality of discharge elements;

a first transistor; and

a plurality of second transistors, wherein

one of a source and drain of the first transistor is electrically connected to a first power supply node,

the other of the source and drain of the first transistor is electrically connected to one node of each of the plurality of discharge elements,

the other node of each of the plurality of discharge elements is electrically isolated from each other and electrically connected to one of a source and drain of corresponding one of the plurality of second transistors,

the other of the source and drain of each of the plurality of second transistors is electrically connected to a second power supply node,

gates of the plurality of second transistors are electrically isolated from each other, and

the first transistor is disposed between the plurality of discharge elements and the plurality of second transistors.

18. The liquid discharge substrate according to claim 17 , wherein an effective channel width We and an effective channel length Lc of the first transistor, and an effective channel width Wi and an effective channel length Li of the second transistor satisfy an expression (1):

Wc/Lc>Wi/Li   (1).

19. A liquid discharge substrate comprising:

a plurality of discharge elements;

a first transistor; and

a plurality of second transistors, wherein

one of a source and drain of the first transistor is electrically connected to a first power supply node,

the other of the source and drain of the first transistor is electrically connected to one node of each of the plurality of discharge elements,

the other node of each of the plurality of discharge elements is electrically isolated from each other and electrically connected to one of a source and drain of corresponding one of the plurality of second transistors,

the other of the source and drain of each of the plurality of second transistors is electrically connected to a second power supply node,

gates of the plurality of second transistors are electrically isolated from each other,

the first transistor is disposed between the plurality of discharge elements and the plurality of second transistors,

an effective channel width Wc and an effective channel length Lc of the first transistor and an effective channel width Wi and an effective channel length Li of the second transistor satisfy an expression (1):

Wc/Lc>Wi/Li   (1),

the liquid discharge substrate further includes

a first wiring extending along a first direction in which the plurality of discharge elements are arranged, and forming the first power supply node, and

a second wiring extending along the first direction and forming the second power supply node,

the first wiring is disposed between the plurality of discharge elements and the second wiring as viewed in plan,

a width W 1 of the first wiring in a second direction intersecting the first direction is smaller than a width W 2 of the second wiring along the second direction, and

the first transistor forms a source follower.