IP Library Granted Patent US 9,478,188
Granted Patent B1
US 9,478,188 · App. 14/978,784 · Granted Oct 25, 2016

Digitally controlled voltage generator

Inventor: Jonathan Chang (San Francisco, CA)
Assignee: IML International
G09G3/3696G09G3/3655H03K19/0005H03M1/66
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Quick Facts
Patent No.
US 9,478,188
App. No.
14/978,784
Granted
Oct 25, 2016
Kind
B1
Abstract

A digitally controlled voltage generator is disclosed for use in applications requiring fine resolution voltage control, such as generating a common voltage for a liquid crystal display. A constant resistance digital to analog converter (DAC) is configured to provide appropriate voltage steps by tuning bias resistors to generate desirable reference voltages for the DAC. The bias resistors are configured to be tuned after placement and routing steps in an integrated circuit design.

Claims (47)

1. A method comprising:

providing a digital-to-analog converter (DAC) for generating an output voltage, wherein the digital-to-analog converter comprises a first at least a first DAC impedance and a second DAC impedance coupled in series between a DAC first node and a DAC second node;

providing a first impedance and a second impedance coupled in series between a reference voltage and ground, wherein a first node is between the first impedance and the second impedance;

providing a third impedance coupled between the first node and the DAC first node of the digital-to-analog converter; and

providing a fourth impedance coupled between the DAC second node of the digital-to-analog converter and ground, and the fourth impedance is not in series with the second impedance.

2. The method of claim 1 wherein the digital-to-analog converter comprises an impedance network and a plurality of gates that are controlled to generate the output voltage at a desired level.

3. The method of claim 2 wherein the gates are controlled in accordance with a fixed-length integer value.

4. The method of claim 2 wherein the impedance network comprises a linear string of serially coupled impedances.

5. The method of claim 2 wherein the impedance network comprises a plurality of impedance segments, each having a string of serially coupled impedances.

6. The method of claim 1 wherein the digital-to-analog converter comprises an impedance network.

7. The method of claim 1 comprising:

providing a digital-to-analog decoder that is coupled to the digital-to-analog converter.

8. The method of claim 1 comprising:

providing a first amplifier comprising a first input coupled to the output voltage of the digital-to-analog converter; and

providing a transistor comprising a gate coupled to an output of the first amplifier and a source node coupled to a second input of the first amplifier.

9. The method of claim 8 comprising:

providing a sixth impedance coupled between the second input of the first amplifier and ground.

10. The method of claim 8 comprising:

providing a second amplifier comprising a first input coupled to a drain node of the transistor, and an output coupled to a second input of the second amplifier.

11. The method of claim 10 comprising:

providing a fifth impedance and a sixth impedance coupled in series between the reference voltage and ground, wherein a second node is between the fifth impedance and the sixth impedance, and the second node is coupled to the first input of the second amplifier.

12. A method of operating an LCD display device comprising the method of claim 10 wherein the output of the second amplifier is coupled to a VCOM voltage node of the LCD display device.

13. The method of claim 1 wherein the second impedance is coupled to ground.

14. The method of claim 1 wherein the second impedance is different from the fourth impedance.

15. A method comprising:

providing a digital-to-analog converter for generating an output voltage;

providing a first impedance and a second impedance coupled in series between a reference voltage and ground, wherein a first node is between the first impedance and the second impedance;

providing a third impedance coupled between the first node and the digital-to-analog converter;

providing a fourth impedance coupled between the digital-to-analog converter and ground;

providing a first amplifier comprising a first input coupled to the output voltage of the digital-to-analog converter;

providing a transistor comprising a gate coupled to an output of the first amplifier and a source node coupled to a second input of the first amplifier;

providing a fifth impedance coupled between the second input of the first amplifier and ground;

providing a second amplifier comprising a first input coupled to a drain node of the transistor, and an output coupled to a second input of the second amplifier; and

providing a sixth impedance and a seventh impedance coupled in series between the reference voltage and ground, wherein a second node is between the sixth impedance and the seventh impedance, and the second node is coupled to the first input of the second amplifier.

16. The method of claim 15 wherein the digital-to-analog converter comprises an impedance network and a plurality of gates that are controlled to generate the output voltage at a desired level.

17. The method of claim 16 wherein the impedance network comprises a linear string of serially coupled impedances.

18. The method of claim 16 wherein the impedance network comprises a plurality of impedance segments, each having a string of serially coupled impedances.

19. The method of claim 16 wherein the gates are controlled in accordance with a fixed-length integer value.

20. The method of claim 15 wherein the digital-to-analog converter comprises an impedance network.

21. A method of operating an LCD display device comprising the method of claim 15 wherein the output of the second amplifier is coupled to a VCOM voltage node of the LCD display device.

22. A method of tuning a voltage generator for a digital-to-analog converter that includes a digital-to-analog converter (DAC) connected at a first node to a first reference voltage level through a first impedance and to ground through a second impedance, the method comprising:

computing a first nominal impedance value for the first impedance;

computing a second nominal impedance value for the second impedance;

adjusting an impedance of the first impedance according to the first nominal impedance value; and

adjusting an impedance of the second impedance according to the second nominal impedance value,

wherein the digital-to-analog converter comprises a second node, and a plurality of DAC impedances are coupled between the first and second nodes, and

a third impedance is coupled between the second node and ground, the third impedance is different from the second impedance, and the third impedance is not in series with the second impedance.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 30, 2021
From: CHANG, JONATHAN
To: IML INTERNATIONAL
Reel/Frame 056107/0822 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 30, 2021
From: IML INTERNATIONAL
To: IML HONGKONG LIMITED
Reel/Frame 056107/0832 →
Continuity (3)
Continuation 14685412 · Apr 13, 2015
Continuation 14288311 · May 27, 2014
Division 12689194 · Jan 18, 2010