IP Library Granted Patent US 9,478,443
Granted Patent B2
US 9,478,443 · App. 14/723,552 · Granted Oct 25, 2016

Semiconductor package and method of forming the same

Inventors: An-Jhih Su (Taoyuan County, TW); Hsien-Wei Chen (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company Limited
H01L21/565H01L23/49811H01L23/5389H01L24/19H01L25/105H01L25/50H01L21/486H01L23/3128H01L23/49822H01L23/50H01L23/5383H01L25/0657H01L25/16H01L2224/01H01L2224/04105H01L2224/12105H01L2224/16265H01L2224/32145H01L2224/32225H01L2224/32265H01L2224/73204H01L2224/73209H01L2224/73217H01L2224/73265H01L2224/73267H01L2224/81005H01L2224/83005H01L2224/92124H01L2224/92244H01L2225/0651H01L2225/06568H01L2225/1035H01L2225/1041H01L2225/1058H01L2924/15311H01L2924/19011H01L2924/19104H01L2924/19105
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,478,443
App. No.
14/723,552
Granted
Oct 25, 2016
Kind
B2
Abstract

According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a chip having a plurality of joint pads; a component having a plurality of metal caps on one side and having a grinded surface on the other side, wherein the metal caps are in contact with the joint pads of the chip.

Claims (32)

1. A semiconductor package, comprising:

a chip having a plurality of joint pads;

a pillar formed on the chip, the pillar having a thickness that is greater than that of the joint pads;

a component having a plurality of metal caps in physical contact with the joint pads of the chip; and

a redistribution layer formed in an insulator layer and including a conductive material that is electrically connected to the chip through the pillar, wherein a distance between the insulator layer and the chip is equal to the thickness of the pillar.

2. The semiconductor package of claim 1 , wherein the component comprises an integrated passive device.

3. The semiconductor package of claim 1 , wherein the component has a thickness of about 30 micrometers to 80 micrometers.

4. The semiconductor package of claim 1 , wherein the component has the metal caps on one side and a grinded surface on the other side.

5. A semiconductor package, comprising:

a chip having a plurality of joint pads;

a pillar formed on the chip, the pillar having a thickness that is greater than that of the joint pads;

a component having a plurality of metal caps on one side and having a grinded surface on the other side, wherein the metal caps are in physical contact with the joint pads of the chip; and

a redistribution layer formed in an insulator layer, the redistribution layer being electrically connected to the chip through the pillar, wherein a distance between the insulator layer and the chip is equal to the thickness of the pillar.

6. The semiconductor package of claim 5 , wherein the component comprises an integrated passive device.

7. The semiconductor package of claim 5 , further comprising an underfill that surrounds the joint pads and the metal caps of the component.

8. The semiconductor package of claim 5 , wherein the component has a thickness of about 30 micrometers to 80 micrometers.

9. The semiconductor package of claim 5 , wherein the component electrically connects to the chip through the metal caps and the joint pads.

10. A semiconductor package, comprising:

a chip having a plurality of joint pads;

a pillar formed on the chip, the pillar having a thickness that is greater than that of the joint pads;

a component having a plurality of metal caps in physical contact with the joint pads of the chip;

a redistribution layer formed in an insulator layer and including a conductive material that is electrically connected to the chip through the pillar, wherein a distance between the insulator and the chip is equal to the thickness of the pillar; and

an underfill surrounding the joint pads and the metal caps of the component.

11. The semiconductor package of claim 10 , wherein the component comprises an integrated passive device.

12. The semiconductor package of claim 10 , wherein the component has a thickness of about 30 micrometers to 80 micrometers.

13. The semiconductor package of claim 10 , wherein the component has the metal caps on one side and a grinded surface on the other side.

14. The semiconductor package of claim 10 , wherein the thickness of the joint pads is about 1 micrometer to 8 micrometers.

15. The semiconductor package of claim 10 , wherein the width of the joint pads is about 20 micrometers to 400 micrometers.

16. The semiconductor package of claim 10 , wherein the thickness of the pillar is about 70 micrometers to 200 micrometers.

17. The semiconductor package of claim 10 , wherein the width of the pillar is about 50 micrometers to 300 micrometers.

18. The semiconductor package of claim 10 , the metal caps are made of at least one of solder, nickel, gold, and copper.

19. The semiconductor package of claim 10 , the thickness of the metal caps is about 10 micrometers to 20 micrometers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2015
From: SU, AN-JHIH; CHEN, HSIEN-WEI
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
Reel/Frame 035751/0759 →
Continuity (2)
Continuation In Part 14470999 · Aug 28, 2014
Related Publication 20160064309A1 · Mar 3, 2016